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user? manual printed in japan 8-bit single-chip microcontrollers m pd78064, 78064y subseries m pd78062 m pd78063 m pd78064 m pd78p064 m pd78062y m pd78063y m pd78064y m pd78p064y document no. u10105ej4v1um00 (4th edition) date published november 1999 n cp(k) 1993
users manual u10105ej4v1um00 [memo]
users manual u10105ej4v1um00 fip is a trademark of nec corporation. iebus, qtop are trademarks of nec corporation. ms-dos and windows are trademarks of microsoft corporation. ibm dos, pc/at and pc dos are trademarks of ibm corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
users manual u10105ej4v1um00 license not needed: m pd78p064kl-t, 78p064ykl-t the customer must judge the need for license: m pd78062gc- x x x -7ea, 78062ygc- x x x -7ea, m pd78062gf- x x x -3ba, 78062ygf- x x x -3ba, m pd78063gc- x x x -7ea, 78063ygc- x x x -7ea, m pd78063gf- x x x -3ba, 78063ygf- x x x -3ba, m pd78064gc- x x x -7ea, 78064ygc- x x x -7ea, m pd78064gf- x x x -3ba, 78064ygf- x x x -3ba, m pd78p064gc-7ea, 78p064ygc-7ea, m pd78p064gf-3ba, 78p064ygf-3ba the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.
users manual u10105ej4v1um00 the application circuits and their parameters are for references only and are not intended for use in actual design- in's. purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7d 98.12
users manual u10105ej4v1um00 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j99.1
users manual u10105ej4v1um00 major revised points (1/2) page revisions throughout m pd78064y subseries has been added for target devices. p.8 section 1.5 "78k/0 series expansion" has been modified. p.36 table 3-1. "pin input/output circuit types" has beem modified. ? recommended connections of the following unused pins p07/xt1, p110 to p117, v pp ? input/output circuit type of the following pins p110 to p117 p.108 pm2 given in figure 6-17. "port mode register format" has been modified. p.117 a caution given in figure 7-4. "oscillation mode selection register format" has been modified and added. p.118 a caution given in figure 7-6. "external circuit of main system clock oscillator" has been modified. p.121 section 7.4.4 "when no subsystem clocks are used" has been modified. connection of xt1 pin: connect to v ss -> connect to v dd . p.197 figure 10-1. "watch timer block diagram" has been modified. p.223 figure 14-2. "a/d converter mode register format" has been modified. p.233 section 14.5(7) "av dd pin" has been modified and figure 14-12. "handling of av dd pin" has been added. p.244 figure 15-4. "serial operating mode register 0 format" has been modified. p.261 figure 15-18. "acknowledge signal" has been modified. p.267 figure 15-21. "reld and cmdd operations (slave)" has been modified. p.284 section 15.4.4(c) "interrupt timing specify register (sint)" has been modified. p.287 figure 15-34. "sck0/p27 pin configuration" has been modified. p.339 figure 17-1. "serial interface channel 2 block diagram" has been modified. p.348 range of baud rate transmit/receive clock generated by main systm clock has been changed. 75 bps to 38400 bps -> 75 bps to 76800 bps p.429 table 20-1. "halt mode operating status" has been modified. description of halt mode operating status has been separated to those during main system clock execution and during sub-system clock execution. p.432 cautions given in section 20.2.2(1) "stop mode set and operating status" have been modified. p.432 table 20-3. "stop mode operating status" has been modified. description of stop mode operating status has been separated to those during main system clock execution and during sub-system clock execution.
users manual u10105ej4v1um00 (2/2) page revisions p.448 description of qtop microcontroller has been added to section 22.5 "screening of one- time prom versions". p.465, 475 hp9000 series 700 has been added for the host machine of development tools and embedded software. p.469 system simulator (sm78k0) has been added for development tools. p.470 section a.4 "operating system for ibm pc" has been added. p.476 os(mx78k0) has been added for embedded software. the asterisks on page margins show revised points.
users manual u10105ej4v1um00 preface readers this manual has been prepared for user engineers who want to understand the functions of the m pd78064 and 78064y subseries and design and develop its application systems and programs. l m pd78064 subseries : m pd78062, 78063, 78064, 78p064 l m pd78064y subseries : m pd78062y, 78063y, 78064y, 78p064 note note under development purpose this manual is intended for users to understand the functions described in the organization below. organization the m pd78064, 78064y subseries manual is separated into two parts: this manual and the instruction edition (common to the 78k/0 series). m pd78064, 78064y 78k/0 series subseries users manual users manual instruction l pin functions l cpu functions l internal block functions l instruction set l interrupt l explanation of each instruction l other on-chip peripheral functions how to read this manual before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. l l when you want to understand the functions in general: ? read this manual in the order of the contents. l l how to interpret the register format: ? for the circled bit number, the bit name is defined as a reserved word in ra78k/ 0, and in cc78k/0, already defined in the header file named sfrbit.h. l l when you know a register name and want to confirm its details: ? read appendix c register index . l l to know the m pd78064 and 78064y subseries instruction function in detail: ? refer to the 78k/0 series user's manual: instructions (ieu-1372) l l to know the electrical specifications of the m pd78064 and 78064y subseries: ? refer to separately available data sheet m pd78062, 78063 and 78064 (ic-3244), m pd78p064 data sheet (ic-3224) m pd78062y, 78063y, 78064y data sheet (ic-3235) l l to know the application example of each function of the m pd78064 and 78064y subseries: ? refer to separately available application note 78k/0 series: basic (iii) (in preparation), 78k/0 series application note: floating-point operation program (iea- 1289)
users manual u10105ej4v1um00 chapter organization : this manual divides the descriptions for the m pd78064 and 78064y subseries into different chapters as shown below. read only the chapters related to the device you use. chapter m pd78064 m pd78064y subseries subseries chapter 1 outline ( m pd78064 subseries) chapter 2 outline ( m pd78064y subseries) chapter 3 pin function ( m pd78064 subseries) chapter 4 pin function ( m pd78064y subseries) chapter 5 cpu architecture ? chapter 6 port functions ? chapter 7 clock generator ? chapter 8 16-bit timer/event counter ? chapter 9 8-bit timer/event counters 1 and 2 ? chapter 10 watch timer ? chapter 11 watchdog timer ? chapter 12 clock output control circuit ? chapter 13 buzzer output control circuit ? chapter 14 a/d converter ? chapter 15 serial interface channel 0 ( m pd78064 subseries) chapter 16 serial interface channel 0 ( m pd78064y subseries) chapter 17 serial interface channel 2 ? chapter 18 lcd controller / driver ? chapter 19 interrupt and test functions ? chapter 20 standby function ? chapter 21 reset function ? chapter 22 m pd78p064, m pd78p064y ? chapter 23 instruction set ?
users manual u10105ej4v1um00 differences between m pd78064 and m pd78064y subseries: the m pd78064 and m pd78064y subseries are different in the following functions of the serial interface channel 0. modes of serial interface channel 0 m pd78064 m pd78064y subseries subseries 3-wire serial i/o mode ? 2-wire serial i/o mode ? sbi (serial bus interface) mode i 2 c (inter ic) bus mode : supported : not supported legend data representation weight : high digits on the left and low digits on the right active low representations : (line over the pin and signal names) note : description of note in the text. caution : information requiring particular attention remarks : additional explanatory material numeral representations : binary ... or b decimal ... hexadecimal ... h
users manual u10105ej4v1um00 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. l related documents for m pd78064 subseries document name document no. english japanese m pd78062, 78063, 78064 data sheet u12338e u12338j m pd78p064 data sheet u12589e u12589j m pd78064, 78064y subseries users manual this manual u10105j 78k/0 series users manualinstruction u12326e u12326j m pd78064, 78064b subseries special function register table u12696j 78k/0 series application note basics iii u10182e u10182j floating-point operation program iea-1289 u13482j l related documents for m pd78064y subseries document name document no. english japanese m pd78062y, 78063y, 78064y data sheet u10337e u10337j m pd78p064y preliminary product information ip-3236 u10321j m pd78064, 78064y subseries users manual this manual u10105j 78k/0 series users manualinstruction u12326e u12326j m pd78064y subseries special function register table iem-5583 78k/0 series application note basics iii u10182e u10182j floating-point operation program iea-1289 u13482j caution the above documents are subject to change without prior notice. be sure to use the latest version document when starting design.
users manual u10105ej4v1um00 l development tool documents (users manuals) document name document no. english japanese ra78k0 assembler package operation u11802e u11802j language u11801e u11801j structured assembly language u11789e u11789j ra78k series structured assembler preprocessor eeu-1402 u12323j cc78k0 c compiler operation u11517e u11517j language u11518e u11518j pg-1500 prom programmer u11940e u11940j pg-1500 controller pc-9800 series (ms-dos tm ) base eeu-1291 eeu-704 pg-1500 controller ibm pc series (pc dos tm ) base u10540e eeu-5008 ie-78000-r u11376e u11376j ie-78000-r-bk eeu-1427 eeu-867 ie-78064-r-em eeu-1443 eeu-905 ep-78064 eeu-1469 eeu-934 sm78k0 system simulator windows based reference u10181e u10181j sm78k series system simulator external part user open u10092e u10092j interface specifications id78k0-ns integrated debugger, windows based reference u12900j id78k0 integrated debugger, ews based reference u11151j id78k0 integrated debugger, windows based guide u11649e u11649j id78k0 integrated debugger, pc based reference u11539e u11539j caution the above documents are subject to change without prior notice. be sure to use the latest version document when starting design.
users manual u10105ej4v1um00 l documents for embedded software (user's manual) document name document no. english japanese 78k/0 series real-time os fundamentals u11537e u11537j installation u11536e u11536j 78k/0 series os mx78k0 fundamental u12257e u12257j l other documents document name document no. english japanese semiconductors selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor devices c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e c11892j review of quality and reliability handbook c12769j guide to microcomputer-related products by third party u11416j caution the above documents are subject to change without prior notice. be sure to use the latest version document when starting design.
users manual u10105ej4v1um00 contents chapter 1 outline ( m pd78064 subseries) .............................................................................. 1 1.1 features ............................................................................................................................. 1 1.2 applications ...................................................................................................................... 2 1.3 ordering information ...................................................................................................... 2 1.4 pin configuration (top view) ........................................................................................ 3 1.5 78k/0 series expansion .................................................................................................. 8 1.6 block diagram .................................................................................................................. 10 1.7 outline of function .......................................................................................................... 11 1.8 mask options ................................................................................................................... 12 chapter 2 outline ( m pd78064y subseries) ............................................................................ 13 2.1 features ............................................................................................................................. 13 2.2 applications ...................................................................................................................... 14 2.3 ordering information ...................................................................................................... 14 2.4 pin configuration (top view) ........................................................................................ 15 2.5 78k/0 series expansion .................................................................................................. 20 2.6 block diagram .................................................................................................................. 22 2.7 outline of function .......................................................................................................... 23 2.8 mask options ................................................................................................................... 24 chapter 3 pin function ( m pd78064 subseries) .................................................................. 25 3.1 pin function list .............................................................................................................. 25 3.1.1 normal operating mode pins .............................................................................................. 25 3.1.2 prom programming mode pins ( m pd78p064 only) ......................................................... 28 3.2 description of pin functions .......................................................................................... 29 3.2.1 p00 to p05, p07 (port 0) .................................................................................................... 29 3.2.2 p10 to p17 (port 1) ............................................................................................................. 30 3.2.3 p25 to p27 (port 2) ............................................................................................................. 30 3.2.4 p30 to p37 (port 3) ............................................................................................................. 31 3.2.5 p70 to p72 (port 7) ............................................................................................................. 32 3.2.6 p80 C p87 (port 8) .............................................................................................................. 33 3.2.7 p90 C p97 (port 9) .............................................................................................................. 33 3.2.8 p100 C p103 (port 10) ........................................................................................................ 33 3.2.9 p110 C p117 (port 11) ........................................................................................................ 33 3.2.10 com0 to com3 ................................................................................................................. 34 3.2.11 v lc0 C v lc2 ........................................................................................................................... 34 3.2.12 bias ............................................................................................................................... ...... 34 3.2.13 av ref ............................................................................................................................... ..... 34 3.2.14 av dd ............................................................................................................................... ...... 34 3.2.15 av ss ............................................................................................................................... ...... 34 3.2.16 reset ............................................................................................................................... ... 34
users manual u10105ej4v1um00 3.2.17 x1 and x2 ............................................................................................................................ 34 3.2.18 xt1 and xt2 ........................................................................................................................ 34 3.2.19 v dd ............................................................................................................................... ........ 35 3.2.20 v ss ............................................................................................................................... ........ 35 3.2.21 v pp ( m pd78p064 only) ......................................................................................................... 35 3.2.22 ic (mask rom version only) .............................................................................................. 35 3.3 input/output circuits and recommended connection of unused pins .................. 36 chapter 4 pin function ( m pd78064y subseries) ................................................................. 41 4.1 pin function list .............................................................................................................. 41 4.1.1 normal operating mode pins .............................................................................................. 41 4.1.2 prom programming mode pins ( m pd78p064y only) ....................................................... 44 4.2 description of pin functions .......................................................................................... 45 4.2.1 p00 to p05, p07 (port 0) .................................................................................................... 45 4.2.2 p10 to p17 (port 1) ............................................................................................................. 46 4.2.3 p25 to p27 (port 2) ............................................................................................................. 46 4.2.4 p30 to p37 (port 3) ............................................................................................................. 47 4.2.5 p70 to p72 (port 7) ............................................................................................................. 48 4.2.6 p80 C p87 (port 8) .............................................................................................................. 49 4.2.7 p90 C p97 (port 9) .............................................................................................................. 49 4.2.8 p100 C p103 (port 10) ........................................................................................................ 49 4.2.9 p110 C p117 (port 11) ........................................................................................................ 49 4.2.10 com0 to com3 ................................................................................................................. 50 4.2.11 v lc0 C v lc2 ........................................................................................................................... 50 4.2.12 bias ............................................................................................................................... ...... 50 4.2.13 av ref ............................................................................................................................... ..... 50 4.2.14 av dd ............................................................................................................................... ...... 50 4.2.15 av ss ............................................................................................................................... ...... 50 4.2.16 reset ............................................................................................................................... ... 50 4.2.17 x1 and x2 ............................................................................................................................ 50 4.2.18 xt1 and xt2 ........................................................................................................................ 50 4.2.19 v dd ............................................................................................................................... ........ 51 4.2.20 v ss ............................................................................................................................... ........ 51 4.2.21 v pp ( m pd78p064y only) ...................................................................................................... 51 4.2.22 ic (mask rom version only) .............................................................................................. 51 4.3 input/output circuits and recommended connection of unused pins .................. 52 chapter 5 cpu architecture ................................................................................................. 57 5.1 memory spaces ................................................................................................................ 57 5.1.1 internal program memory space ........................................................................................ 61 5.1.2 internal data memory space .............................................................................................. 62 5.1.3 special function register (sfr) area ................................................................................ 62 5.1.4 data memory addressing ................................................................................................... 63 5.2 processor registers ......................................................................................................... 67 5.2.1 control registers ................................................................................................................. 67 5.2.2 general registers ................................................................................................................ 69 5.2.3 special function register (sfr) ......................................................................................... 71
users manual u10105ej4v1um00 5.3 instruction address addressing ................................................................................... 75 5.3.1 relative addressing ............................................................................................................ 75 5.3.2 immediate addressing ........................................................................................................ 76 5.3.3 table indirect addressing ................................................................................................... 77 5.3.4 register addressing ............................................................................................................ 78 5.4 operand address addressing ........................................................................................ 79 5.4.1 implied addressing .............................................................................................................. 79 5.4.2 register addressing ............................................................................................................ 80 5.4.3 direct addressing ................................................................................................................ 81 5.4.4 short direct addressing ...................................................................................................... 82 5.4.5 special-function register (sfr) addressing ...................................................................... 84 5.4.6 register indirect addressing .............................................................................................. 85 5.4.7 based addressing ............................................................................................................... 86 5.4.8 based indexed addressing ................................................................................................. 87 5.4.9 stack addressing ................................................................................................................. 87 chapter 6 port functions ..................................................................................................... 89 6.1 port functions .................................................................................................................. 89 6.2 port configuration ........................................................................................................... 92 6.2.1 port 0 ............................................................................................................................... .... 92 6.2.2 port 1 ............................................................................................................................... .... 94 6.2.3 port 2 ( m pd78064 subseries) ............................................................................................. 95 6.2.4 port 2 ( m pd78064y subseries) .......................................................................................... 97 6.2.5 port 3 ............................................................................................................................... .... 99 6.2.6 port 7 ............................................................................................................................... .... 100 6.2.7 port 8 ............................................................................................................................... .... 102 6.2.8 port 9 ............................................................................................................................... .... 103 6.2.9 port 10 ............................................................................................................................... .. 104 6.2.10 port 11 ............................................................................................................................... .. 105 6.3 port function control registers .................................................................................... 106 6.4 port function operations ............................................................................................... 111 6.4.1 writing to input/output port ............................................................................................... 111 6.4.2 reading from input/output port ......................................................................................... 111 6.4.3 operations on input/output port ........................................................................................ 111 chapter 7 clock generator ................................................................................................. 113 7.1 clock generator functions ............................................................................................. 113 7.2 clock generator configuration ...................................................................................... 113 7.3 clock generator control register ................................................................................. 115 7.4 system clock oscillator .................................................................................................. 118 7.4.1 main system clock oscillator .............................................................................................. 118 7.4.2 subsystem clock oscillator ................................................................................................. 119 7.4.3 scaler ............................................................................................................................... .... 121 7.4.4 when no subsystem clocks are used ............................................................................... 121 7.5 clock generator operations ........................................................................................... 122 7.5.1 main system clock operations ........................................................................................... 123 7.5.2 subsystem clock operations .............................................................................................. 124
users manual u10105ej4v1um00 7.6 changing system clock and cpu clock settings ....................................................... 125 7.6.1 time required for switchover between system clock and cpu clock ............................. 125 7.6.2 system clock and cpu clock switching procedure .......................................................... 126 chapter 8 16-bit timer/event counter ............................................................................. 127 8.1 16-bit timer/event counter functions ......................................................................... 129 8.2 16-bit timer/event counter configuration .................................................................. 131 8.3 16-bit timer/event counter control registers ........................................................... 135 8.4 16-bit timer/event counter operations ....................................................................... 144 8.4.1 interval timer operations .................................................................................................... 144 8.4.2 pwm output operations ..................................................................................................... 146 8.4.3 ppg output operations ....................................................................................................... 149 8.4.4 pulse width measurement operations ............................................................................... 150 8.4.5 external event counter operation ....................................................................................... 157 8.4.6 square-wave output operation ........................................................................................... 159 8.4.7 one-shot pulse output operation ....................................................................................... 161 8.5 16-bit timer/event counter operating precautions .................................................. 165 chapter 9 8-bit timer/event counters 1 and 2 ............................................................. 169 9.1 8-bit timer/event counters 1 and 2 functions ........................................................... 169 9.1.1 8-bit timer/event counter mode ......................................................................................... 169 9.1.2 16-bit timer/event counter mode ....................................................................................... 172 9.2 8-bit timer/event counters 1 and 2 configurations .................................................. 174 9.3 8-bit timer/event counters 1 and 2 control registers ............................................. 178 9.4 8-bit timer/event counters 1 and 2 operations ........................................................ 183 9.4.1 8-bit timer/event counter mode ......................................................................................... 183 9.4.2 16-bit timer/event counter mode ....................................................................................... 188 9.5 cautions on 8-bit timer/event counters 1 and 2 ....................................................... 192 chapter 10 watch timer ......................................................................................................... 195 10.1 watch timer functions ................................................................................................... 195 10.2 watch timer configuration ............................................................................................ 196 10.3 watch timer control registers ..................................................................................... 196 10.4 watch timer operations ................................................................................................. 200 10.4.1 watch timer operation ........................................................................................................ 200 10.4.2 interval timer operation ...................................................................................................... 200 chapter 11 watchdog timer ................................................................................................. 201 11.1 watchdog timer functions ............................................................................................ 201 11.2 watchdog timer configuration ..................................................................................... 203 11.3 watchdog timer control registers ............................................................................... 204 11.4 watchdog timer operations .......................................................................................... 207 11.4.1 watchdog timer operation ................................................................................................. 207 11.4.2 interval timer operation ...................................................................................................... 208
users manual u10105ej4v1um00 chapter 12 clock output control circuit .................................................................... 209 12.1 clock output control circuit functions ....................................................................... 209 12.2 clock output control circuit configuration ................................................................ 210 12.3 clock output function control registers .................................................................... 211 chapter 13 buzzer output control circuit .................................................................. 215 13.1 buzzer output control circuit functions ..................................................................... 215 13.2 buzzer output control circuit configuration .............................................................. 215 13.3 buzzer output function control registers .................................................................. 216 chapter 14 a/d converter ..................................................................................................... 219 14.1 a/d converter functions ................................................................................................ 219 14.2 a/d converter configuration ......................................................................................... 219 14.3 a/d converter control registers .................................................................................. 222 14.4 a/d converter operations .............................................................................................. 226 14.4.1 basic operations of a/d converter ..................................................................................... 226 14.4.2 input voltage and conversion results ................................................................................. 228 14.4.3 a/d converter operating mode ........................................................................................... 229 14.5 a/d converter cautions .................................................................................................. 231 chapter 15 serial interface channel 0 ( m pd78064 subseries) .................................... 235 15.1 serial interface channel 0 functions ............................................................................ 236 15.2 serial interface channel 0 configuration ..................................................................... 238 15.3 serial interface channel 0 control registers .............................................................. 242 15.4 serial interface channel 0 operations .......................................................................... 249 15.4.1 operation stop mode .......................................................................................................... 249 15.4.2 3-wire serial i/o mode operation ....................................................................................... 250 15.4.3 sbi mode operation ............................................................................................................ 255 15.4.4 2-wire serial i/o mode operation ....................................................................................... 281 15.4.5 sck0/p27 pin output manipulation .................................................................................... 287 chapter 16 serial interface channel 0 ( m pd78064y subseries) ................................. 289 16.1 serial interface channel 0 functions ............................................................................ 290 16.2 serial interface channel 0 configuration ..................................................................... 292 16.3 serial interface channel 0 control registers .............................................................. 296 16.4 serial interface channel 0 operations .......................................................................... 303 16.4.1 operation stop mode .......................................................................................................... 303 16.4.2 3-wire serial i/o mode operation ....................................................................................... 304 16.4.3 2-wire serial i/o mode operation ....................................................................................... 308 16.4.4 i 2 c bus mode operation ..................................................................................................... 314 16.4.5 cautions on use of i 2 c bus mode ..................................................................................... 331 16.4.6 sck0/scl/p27 pin output manipulation ............................................................................ 334
users manual u10105ej4v1um00 chapter 17 serial interface channel 2 ........................................................................... 337 17.1 serial interface channel 2 functions ............................................................................ 337 17.2 serial interface channel 2 configuration ..................................................................... 338 17.3 serial interface channel 2 control registers .............................................................. 342 17.4 serial interface channel 2 operation ............................................................................ 350 17.4.1 operation stop mode .......................................................................................................... 350 17.4.2 asynchronous serial interface (uart) mode .................................................................... 352 17.4.3 3-wire serial i/o mode ........................................................................................................ 365 chapter 18 lcd controller/driver ................................................................................. 371 18.1 lcd controller/driver functions ................................................................................... 371 18.2 lcd controller/driver configuration ............................................................................ 372 18.3 lcd controller/driver control registers ...................................................................... 374 18.4 lcd controller/driver settings ...................................................................................... 377 18.5 lcd display data memory ............................................................................................. 378 18.6 common signals and segment signals ....................................................................... 379 18.7 supply of lcd drive voltages v lc0 , v lc1 , v lc2 ........................................................................ 383 18.8 display modes .................................................................................................................. 387 18.8.1 static display example ....................................................................................................... 387 18.8.2 2-time-division display example ....................................................................................... 390 18.8.3 3-time-division display example ....................................................................................... 393 18.8.4 4-time-division display example ....................................................................................... 397 chapter 19 interrupt and test functions .................................................................... 401 19.1 interrupt function types ................................................................................................ 401 19.2 interrupt sources and configuration ............................................................................ 402 19.3 interrupt function control registers ............................................................................ 405 19.4 interrupt servicing operations ...................................................................................... 414 19.4.1 non-maskable interrupt acknowledge operation ............................................................... 414 19.4.2 maskable interrupt acknowledge operation ...................................................................... 417 19.4.3 software interrupt acknowledge operation ....................................................................... 420 19.4.4 multiple interrupt servicing ................................................................................................ 420 19.4.5 interrupt reserve ................................................................................................................. 422 19.5 test functions .................................................................................................................. 423 19.5.1 registers controlling the test function .............................................................................. 423 19.5.2 test input signal acknowledge operation .......................................................................... 426 chapter 20 standby function ............................................................................................ 427 20.1 standby function and configuration ........................................................................... 427 20.1.1 standby function ................................................................................................................. 427 20.1.2 standby function control register ...................................................................................... 428 20.2 standby function operations ........................................................................................ 429 20.2.1 halt mode ......................................................................................................................... 429 20.2.2 stop mode ......................................................................................................................... 432
users manual u10105ej4v1um00 chapter 21 reset function .................................................................................................... 435 21.1 reset function .................................................................................................................. 435 chapter 22 m pd78p064, 78p064y ............................................................................................... 439 22.1 memory size switching register .................................................................................. 440 22.2 prom programming ........................................................................................................ 441 22.2.1 operating modes ................................................................................................................ 441 22.2.2 prom write procedure ...................................................................................................... 443 22.2.3 prom reading procedure ................................................................................................... 447 22.3 erasure procedure ( m pd78p064kl-t and 78p064ykl-t only) ................................... 448 22.4 opaque film masking the window ( m pd78p064kl-t and 78p064ykl-t only) ...... 448 22.5 screening of one-time prom versions ...................................................................... 448 chapter 23 instruction set .................................................................................................. 449 23.1 legends used in operation list .................................................................................... 450 23.1.1 operand identifiers and description methods ................................................................... 450 23.1.2 description of operation column ................................................................................... 451 23.1.3 description of flag operation column ............................................................................ 451 23.2 operation list ................................................................................................................... 452 23.3 instructions listed by addressing type ....................................................................... 460
users manual u10105ej4v1um00 appendix a development tools .......................................................................................... 465 a.1 language processing software ..................................................................................... 466 a.2 prom programming tools ............................................................................................. 467 a.3 debugging tool ................................................................................................................ 468 a.3.1 hardware ............................................................................................................................. 46 8 a.3.2 software .............................................................................................................................. 4 69 a.4 operating systems for ibm pc ...................................................................................... 470 appendix b embedded software ......................................................................................... 475 b.1 real-time os ..................................................................................................................... 475 b.2 fuzzy inference development support system .......................................................... 477 appendix c register index .................................................................................................... 479 c.1 register name index ....................................................................................................... 479 c.2 register symbol index .................................................................................................... 482 appendix d revision history ............................................................................................... 485
users manual u10105ej4v1um00 list of figures (1/8) figure no. title page 3-1 pin input/output circuit of list ............................................................................................ 38 4-1 pin input/output circuit of list ............................................................................................ 54 5-1 memory map ( m pd78062, 78062y) ..................................................................................... 57 5-2 memory map ( m pd78063, 78063y) ..................................................................................... 58 5-3 memory map ( m pd78064, 78064y) ..................................................................................... 59 5-4 memory map ( m pd78p064, 78p064y) ................................................................................. 60 5-5 data memory addressing ( m pd78062, 78062y) ................................................................. 63 5-6 data memory addressing ( m pd78063, 78063y) ................................................................. 64 5-7 data memory addressing ( m pd78064, 78064y) ................................................................. 65 5-8 data memory addressing ( m pd78p064, 78p064y) ............................................................. 66 5-9 program counter configuration ........................................................................................... 67 5-10 program status word configuration .................................................................................... 67 5-11 stack pointer configuration .................................................................................................. 68 5-12 data to be saved to stack memory .................................................................................... 68 5-13 data to be reset from stack memory ................................................................................ 69 5-14 general register configuration ............................................................................................ 70 6-1 port types ............................................................................................................................. 89 6-2 p00 and p07 configurations ................................................................................................. 93 6-3 p01 to p05 configurations ................................................................................................... 93 6-4 p10 to p17 configurations ................................................................................................... 94 6-5 p25, p26 configurations ( m pd78064 subseries) ................................................................. 95 6-6 p27 configuration ( m pd78064 subseries) ............................................................................ 96 6-7 p25, p26 configurations ( m pd78064y subseries) ............................................................... 97 6-8 p27 configuration ( m pd78064y subseries) ......................................................................... 98 6-9 p30 to p37 configurations ................................................................................................... 99 6-10 p70 configuration ................................................................................................................. 100 6-11 p71 and p72 configurations ................................................................................................. 101 6-12 p80 to p87 configurations ................................................................................................... 102 6-13 p90 to p97 configurations ................................................................................................... 103 6-14 p100 to p103 configurations ............................................................................................... 104 6-15 p110 to p117 configurations ............................................................................................... 105 6-16 block diagram of falling edge detection circuit ................................................................ 105 6-17 port mode register format ................................................................................................. 108 6-18 pull-up resistor option register format ............................................................................ 109 6-19 key return mode register format ...................................................................................... 110
users manual u10105ej4v1um00 list of figures (2/8) figure no. title page 7-1 block diagram of clock generator ...................................................................................... 114 7-2 subsystem clock feedback resistor .................................................................................. 115 7-3 processor clock control register format ........................................................................... 116 7-4 oscillation mode selection register format ....................................................................... 117 7-5 main system clock waveform due to writing to osms ................................................... 117 7-6 external circuit of main system clock oscillator ............................................................... 118 7-7 external circuit of subsystem clock oscillator ................................................................... 119 7-8 examples of oscillator with bad connection ...................................................................... 119 7-9 main system clock stop function ...................................................................................... 123 7-10 system clock and cpu clock switching ............................................................................. 126 8-1 16-bit timer/event counter block diagram ........................................................................ 132 8-2 16-bit timer/event counter output control circuit block diagram ................................... 133 8-3 timer clock selection register 0 format ............................................................................ 136 8-4 16-bit timer mode control register format ....................................................................... 138 8-5 capture/compare control register 0 format ...................................................................... 139 8-6 16-bit timer output control register format ..................................................................... 140 8-7 port mode register 3 format .............................................................................................. 141 8-8 external interrupt mode register 0 format ........................................................................ 142 8-9 sampling clock select register format .............................................................................. 143 8-10 control register settings for interval timer operation ...................................................... 144 8-11 interval timer configuration diagram .................................................................................. 145 8-12 interval timer operation timings ........................................................................................ 145 8-13 control register settings for pwm output operation ....................................................... 147 8-14 example of d/a converter configuration with pwm output ............................................ 148 8-15 tv tuner application circuit example ................................................................................. 148 8-16 control register settings for ppg output operation ......................................................... 149 8-17 control register settings for pulse width measurement with free-running counter and one capture register .............................................................. 150 8-18 configuration diagram for pulse width measurement by free-running counter ............ 151 8-19 timing of pulse width measurement operation by free-running counter and one capture register (with both edges specified) .................................................... 151 8-20 control register settings for two pulse width measurements with free-running counter .................................................................................................. 152 8-21 timing of pulse width measurement operation with free-running counter (with both edges specified) ............................................................................................... 153 8-22 control register settings for pulse width measurement with free-running counter and two capture registers .................................................................................................. 154 8-23 timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) ................................... 155 8-24 control register settings for pulse width measurement by means of restart .............. 156 8-25 timing of pulse width measurement operation by means of restart (with rising edge specified) ............................................................................................... 156
users manual u10105ej4v1um00 list of figures (3/8) figure no. title page 8-26 control register settings in external event counter mode ............................................... 157 8-27 external event counter configuration diagram .................................................................. 158 8-28 external event counter operation timings (with rising edge specified) ......................... 158 8-29 control register settings in square-wave output mode .................................................. 159 8-30 square-wave output operation timing .............................................................................. 160 8-31 control register settings for one-shot pulse output operation using software trigger ................................................................................................................... 161 8-32 timing of one-shot pulse output operation using software trigger .............................. 162 8-33 control register settings for one-shot pulse output operation using external trigger .......................................................................................................... 163 8-34 timing of one-shot pulse output operation using external trigger (with rising edge specified) ................................................................................................ 164 8-35 16-bit timer register start timing ...................................................................................... 165 8-36 timings after change of compare register during timer count operation .................... 165 8-37 capture register data retention timing ............................................................................. 166 8-38 operation timing of ovf0 flag ........................................................................................... 167 9-1 8-bit timer/event counters 1 and 2 block diagram ........................................................... 175 9-2 block diagram of 8-bit timer/event counter output control circuit 1 ............................. 176 9-3 block diagram of 8-bit timer/event counter output control circuit 2 ............................. 176 9-4 timer clock select register 1 format ................................................................................ 179 9-5 8-bit timer mode control register format ......................................................................... 180 9-6 8-bit timer output control register format ....................................................................... 181 9-7 port mode register 3 format .............................................................................................. 182 9-8 interval timer operation timings ........................................................................................ 183 9-9 external event counter operation timings (with rising edge specified) ......................... 186 9-10 interval timer operation timing .......................................................................................... 188 9-11 external event counter operation timings (with rising edge specified) ......................... 190 9-12 8-bit timer registers 1 and 2 start timing ......................................................................... 192 9-13 external event counter operation timing ........................................................................... 192 9-14 timing after compare register change during timer count operation ........................... 193 10-1 watch timer block diagram ................................................................................................ 197 10-2 timer clock select register 2 format ................................................................................ 198 10-3 watch timer mode control register format ...................................................................... 199 11-1 watchdog timer block diagram .......................................................................................... 203 11-2 timer clock select register 2 format ................................................................................ 205 11-3 watchdog timer mode register format ............................................................................. 206
users manual u10105ej4v1um00 list of figures (4/8) figure no. title page 12-1 remote controlled output application example ................................................................ 209 12-2 clock output control circuit block diagram ....................................................................... 210 12-3 timer clock select register 0 format ................................................................................ 212 12-4 port mode register 3 format .............................................................................................. 213 13-1 buzzer output control circuit block diagram ..................................................................... 215 13-2 timer clock select register 2 format ................................................................................ 217 13-3 port mode register 3 format .............................................................................................. 218 14-1 a/d converter block diagram .............................................................................................. 220 14-2 a/d converter mode register format ................................................................................. 223 14-3 a/d converter input select register format ...................................................................... 224 14-4 external interrupt mode register 1 format ........................................................................ 225 14-5 a/d converter basic operation ............................................................................................ 227 14-6 relations between analog input voltage and a/d conversion result .............................. 228 14-7 a/d conversion by hardware start ...................................................................................... 229 14-8 a/d conversion by software start ....................................................................................... 230 14-9 example of method of reducing current consumption in standby mode ....................... 231 14-10 analog input pin disposition ................................................................................................ 232 14-11 a/d conversion end interrupt generation timing .............................................................. 233 14-12 handling of av dd pin ............................................................................................................ 233 15-1 serial bus interface (sbi) system configuration example ................................................. 237 15-2 serial interface channel 0 block diagram ............................................................................. 239 15-3 timer clock select register 3 format ................................................................................... 243 15-4 serial operating mode register 0 format ............................................................................. 244 15-5 serial bus interface control register format ........................................................................ 246 15-6 interrupt timing specify register format ............................................................................. 248 15-7 3-wire serial i/o mode timings ............................................................................................ 2 53 15-8 relt and cmdt operations ................................................................................................. 25 3 15-9 circuit of switching in transfer bit order .............................................................................. 254 15-10 example of serial bus configuration with sbi ...................................................................... 255 15-11 sbi transfer timings ...................................................................................................... ....... 257 15-12 bus release signal ........................................................................................................ ........ 258 15-13 command signal ............................................................................................................ ....... 258 15-14 addresses ................................................................................................................. ............ 259 15-15 slave selection with address .............................................................................................. .. 259 15-16 commands .................................................................................................................. .......... 260 15-17 data ...................................................................................................................... ................. 260 15-18 acknowledge signal ........................................................................................................ ...... 261 15-19 busy and ready signals .................................................................................................... . 262 15-20 relt, cmdt, reld, and cmdd operations (master) ......................................................... 267
users manual u10105ej4v1um00 list of figures (5/8) figure no. title page 15-21 reld and cmdd operations (slave) .................................................................................... 267 15-22 ackt operation ............................................................................................................ ......... 268 15-23 acke operations ........................................................................................................... ........ 269 15-24 ackd operations ........................................................................................................... ....... 270 15-25 bsye operation ............................................................................................................ ......... 270 15-26 pin configuration ......................................................................................................... .......... 273 15-27 address transmission from master device to slave device (wup = 1) .............................. 275 15-28 command transmission from master device to slave device ............................................. 276 15-29 data transmission from master device to slave device ...................................................... 277 15-30 data transmission from slave device to master device ...................................................... 278 15-31 serial bus configuration example using 2-wire serial i/o mode ......................................... 281 15-32 2-wire serial i/o mode timings ............................................................................................ 285 15-33 relt and cmdt operations ................................................................................................. 2 86 15-34 sck0/p27 pin configuration ................................................................................................ .. 287 16-1 serial bus configuration example using i 2 c bus .................................................................. 291 16-2 serial interface channel 0 block diagram ............................................................................. 293 16-3 timer clock select register 3 format ................................................................................... 297 16-4 serial operating mode register 0 format ............................................................................. 298 16-5 serial bus interface control register format ........................................................................ 299 16-6 interrupt timing specify register format ............................................................................. 301 16-7 3-wire serial i/o mode timings ............................................................................................ 3 06 16-8 relt and cmdt operations ................................................................................................. 30 6 16-9 circuit of switching in transfer bit order .............................................................................. 307 16-10 serial bus configuration example using 2-wire serial i/o mode ......................................... 308 16-11 2-wire serial i/o mode timings ............................................................................................ 312 16-12 relt and cmdt operations ................................................................................................. 3 13 16-13 example of serial bus configuration using i 2 c bus .............................................................. 314 16-14 i 2 c bus serial data transfer timing ...................................................................................... 315 16-15 start condition ........................................................................................................... ............ 316 16-16 address ................................................................................................................... .............. 316 16-17 transfer direction specification .......................................................................................... .. 316 16-18 acknowledge signal ........................................................................................................ ...... 317 16-19 stop condition ............................................................................................................ ........... 317 16-20 wait signal ............................................................................................................... ............. 318 16-21 pin configuration ......................................................................................................... .......... 323 16-22 data transmission from master to slave (both master and slave selected 9-clock wait) .................................................................... 325 16-23 data transmission from slave to master (both master and slave selected 9-clock wait) .................................................................... 328 16-24 start condition output .................................................................................................... ...... 331 16-25 slave wait release (transmission) ....................................................................................... 33 2
users manual u10105ej4v1um00 list of figures (6/8) figure no. title page 16-26 slave wait release (reception) ............................................................................................ 333 16-27 sck0/scl/p27 pin configuration .......................................................................................... 33 4 16-28 sck0/scl/p27 pin configuration .......................................................................................... 33 5 16-29 logic circuit of scl signal ............................................................................................... ..... 335 17-1 serial interface channel 2 block diagram ............................................................................. 339 17-2 baud rate generator block diagram ..................................................................................... 340 17-3 serial operating mode register 2 format ............................................................................. 342 17-4 asynchronous serial interface mode register format ......................................................... 343 17-5 asynchronous serial interface status register format ......................................................... 345 17-6 baud rate generator control register format ..................................................................... 346 17-7 asynchronous serial interface transmit/receive data format ............................................. 359 17-8 asynchronous serial interface transmission completion interrupt timing .......................... 361 17-9 asynchronous serial interface reception completion interrupt timing ............................... 362 17-10 receive error timing ...................................................................................................... ....... 363 17-11 3-wire serial i/o mode timing ............................................................................................. . 370 18-1 lcd controller/driver block diagram .................................................................................... 372 18-2 lcd clock select circuit block diagram ............................................................................... 373 18-3 lcd display mode register format ...................................................................................... 374 18-4 lcd display control register format ................................................................................... 376 18-5 relationship between lcd display data memory contents and segment/common outputs .................................................................................................. 378 18-6 common signal waveform ................................................................................................... 38 1 18-7 common signal and static signal voltages and phases ....................................................... 382 18-8 lcd drive power supply connection examples (with on-chip split resistor) ..................... 384 18-9 lcd drive power supply connection examples (with external split resistor) ..................... 385 18-10 example of lcd drive voltage supply from off-chip ........................................................... 386 18-11 static lcd display pattern and electrode connections ........................................................ 387 18-12 static lcd panel connection example .................................................................................. 388 18-13 static lcd drive waveform examples .................................................................................. 389 18-14 2-time-division lcd display pattern and electrode connections ......................................... 390 18-15 2-time-division lcd panel connection example .................................................................. 391 18-16 2-time-division lcd drive waveform examples (1/2 bias method) .................................... 392 18-17 3-time-division lcd display pattern and electrode connections ......................................... 393 18-18 3-time-division lcd panel connection example .................................................................. 394 18-19 3-time-division lcd drive waveform examples (1/2 bias method) .................................... 395 18-20 3-time-division lcd drive waveform examples (1/3 bias method) ..................................... 396 18-21 4-time-division lcd display pattern and electrode connections ......................................... 397 18-22 4-time-division lcd panel connection example .................................................................. 398 18-23 4-time-division lcd drive waveform examples (1/3 bias method) .................................... 399
users manual u10105ej4v1um00 list of figures (7/8) figure no. title page 19-1 basic configuration of interrupt function .............................................................................. 403 19-2 interrupt request flag register format ................................................................................ 406 19-3 interrupt mask flag register format .................................................................................... 407 19-4 priority specify flag register format .................................................................................... 40 8 19-5 external interrupt mode register 0 format .......................................................................... 409 19-6 external interrupt mode register 1 format .......................................................................... 410 19-7 sampling clock select register format ................................................................................ 411 19-8 noise remover input/output timing (during rising edge detection) ..................................... 412 19-9 program status word format ............................................................................................... 41 3 19-10 non-maskable interrupt acknowledge flowchart ................................................................. 415 19-11 non-maskable interrupt acknowledge timing ...................................................................... 415 19-12 non-maskable interrupt request acknowledge operation ................................................... 416 19-13 interrupt acknowledge processing algorithm ....................................................................... 418 19-14 interrupt acknowledge timing (minimum time) ................................................................... 419 19-15 interrupt acknowledge timing (maximum time) .................................................................. 419 19-16 multiple interrupt example ................................................................................................ .... 421 19-17 interrupt request hold .................................................................................................... ...... 422 19-18 basic configuration of test function .................................................................................... 42 3 19-19 format of interrupt request flag register 1l ....................................................................... 424 19-20 format of interrupt mask flag register 1l ........................................................................... 424 19-21 key return mode register format ....................................................................................... 425 20-1 oscillation stabilization time select register format ........................................................... 428 20-2 halt mode clear upon interrupt generation ....................................................................... 430 20-3 halt mode release by reset input ................................................................................... 431 20-4 stop mode release by interrupt generation ....................................................................... 433 20-5 release by stop mode reset input ................................................................................... 434 21-1 block diagram of reset function .......................................................................................... 43 5 21-2 timing of reset input by reset input .................................................................................. 436 21-3 timing of reset due to watchdog timer overflow .............................................................. 436 21-4 timing of reset input in stop mode by reset input ......................................................... 436 22-1 memory size switching register format .............................................................................. 440 22-2 page program mode flowchart ............................................................................................. 443 22-3 page program mode timing .................................................................................................. 4 44 22-4 byte program mode flowchart ............................................................................................. 445 22-5 byte program mode timing .................................................................................................. 4 46 22-6 prom read timing ........................................................................................................... .... 447
users manual u10105ej4v1um00 list of figures (8/8) figure no. title page a-1 development tool configuration ........................................................................................... 465 a-2 tgc-100sdw drawing (for reference only) (unit: mm) ..................................................... 472 a-3 ev-9200gf-100 drawing (for reference only) ..................................................................... 473 a-4 ev-9200gf-100 footprint (for reference only) .................................................................... 474
users manual u10105ej4v1um00 list of tables (1/3) table no. title page 1-1 mask options of mask rom versions .................................................................................. 12 2-1 mask options of mask rom versions .................................................................................. 24 3-1 pin input/output circuit types .............................................................................................. 36 4-1 pin input/output circuit types .............................................................................................. 52 5-1 internal rom capacity ....................................................................................................... ... 61 5-2 vector table ................................................................................................................ .......... 61 5-3 internal high-speed ram capacity ....................................................................................... 62 5-4 special-function register list .............................................................................................. .73 6-1 port functions ( m pd78064 subseries) ................................................................................... 90 6-2 port functions ( m pd78064y subseries) ................................................................................. 91 6-3 port configuration .......................................................................................................... ....... 92 6-4 port mode register and output latch settings when using dual-functions ....................... 107 7-1 clock generator configuration .............................................................................................. 1 13 7-2 maximum time required for cpu clock switchover ........................................................... 125 8-1 timer/event counter types and functions ........................................................................... 128 8-2 16-bit timer/event counter interval times ........................................................................... 129 8-3 16-bit timer/event counter square-wave output ranges ................................................... 130 8-4 16-bit timer/event counter configuration ............................................................................ 131 8-5 intp0/ti00 pin valid edge and cr00 capture trigger valid edge ......................................... 134 8-6 16-bit timer/event counter interval times ........................................................................... 146 8-7 16-bit timer/event count square-wave output ranges ...................................................... 160 9-1 8-bit timer/event counters 1 and 2 interval times ............................................................... 170 9-2 8-bit timer/event counters 1 and 2 square-wave output ranges ....................................... 171 9-3 interval times when 8-bit timer/event counters 1 and 2 are used as 16-bit timer/event counters ................................................................................... 172 9-4 square-wave output ranges when 8-bit timer/event counters 1 and 2 are used as 16-bit timer/event counters ............................................................................. 173 9-5 8-bit timer/event counters 1 and 2 configurations .............................................................. 174 9-6 8-bit timer/event counter 1 interval time ............................................................................ 184 9-7 8-bit timer/event counter 2 interval time ............................................................................ 185 9-8 8-bit timer/event counters 1 and 2 square-wave output ranges ....................................... 187 9-9 interval times when 2-channel 8-bit timer/event counters (tm1 and tm2) are used as 16-bit timer/event counter ..................................................... 189 9-10 square-wave output ranges when 2-channel 8-bit timer/event counters (tm1 and tm2) are used as 16-bit timer/event counter ..................................................... 191
users manual u10105ej4v1um00 list of tables (2/3) table no. title page 10-1 interval timer interval time ............................................................................................... .... 195 10-2 watch timer configuration .................................................................................................. . 196 10-3 interval timer interval time ............................................................................................... .... 200 11-1 watchdog timer inadvertent program overrun detection times ......................................... 201 11-2 interval times ............................................................................................................. ........... 202 11-3 watchdog timer configuration ............................................................................................. 20 3 11-4 watchdog timer overrun detection time ............................................................................ 207 11-5 interval timer interval time ............................................................................................... .... 208 12-1 clock output control circuit configuration ........................................................................... 210 13-1 buzzer output control circuit configuration ......................................................................... 215 14-1 a/d converter configuration ................................................................................................ . 219 15-1 differences between channels 0 and 2 ................................................................................ 235 15-2 serial interface channel 0 configuration ............................................................................... 238 15-3 various signals in sbi mode ................................................................................................ . 271 16-1 differences between channels 0 and 2 ................................................................................ 289 16-2 serial interface channel 0 configuration ............................................................................... 292 16-3 serial interface channel 0 interrupt request signal generation ........................................... 295 16-4 signals in i 2 c bus mode ........................................................................................................ 322 17-1 serial interface channel 2 configuration ............................................................................... 338 17-2 serial interface channel 2 operating mode settings ............................................................ 344 17-3 relation between main system clock and baud rate .......................................................... 348 17-4 relation between asck pin input frequency and baud rate (when brgc is set to 00h) .. 349 17-5 relation between main system clock and baud rate .......................................................... 357 17-6 relation between asck pin input frequency and baud rate (when brgc is set to 00h) .. 358 17-7 receive error causes ....................................................................................................... ..... 363 18-1 maximum number of display pixels ..................................................................................... 371 18-2 lcd controller/driver configuration ...................................................................................... 37 2 18-3 frame frequencies (hz) ..................................................................................................... ... 375 18-4 com signals ................................................................................................................ ......... 379 18-5 lcd drive voltages ......................................................................................................... ...... 380 18-6 lcd drive voltages (with on-chip split resistor) ................................................................. 383 18-7 selection and non-selection voltages (com0) ..................................................................... 387 18-8 selection and non-selection voltages (com0, com1) ........................................................ 390 18-9 selection and non-selection voltages (com0 to com2) ..................................................... 393 18-10 selection and non-selection voltages (com0 to com3) ..................................................... 397
users manual u10105ej4v1um00 list of tables (3/3) table no. title page 19-1 interrupt source list ...................................................................................................... ........ 402 19-2 various flags corresponding to interrupt request sources ................................................. 405 19-3 times from maskable interrupt request generation to interrupt service ............................ 417 19-4 interrupt request enabled for multiple interrupt during interrupt servicing ......................... 420 19-5 test input factors ......................................................................................................... ........ 423 19-6 flags corresponding to test input signals ............................................................................ 423 20-1 halt mode operating status ............................................................................................... 42 9 20-2 operation after halt mode release .................................................................................... 431 20-3 stop mode operating status ............................................................................................... 43 2 20-4 operation after stop mode release .................................................................................... 434 21-1 hardware status after reset ................................................................................................ . 437 22-1 differences among m pd78p064, 78p064y and mask rom versions .................................. 439 22-2 examples of memory size switching register settings ....................................................... 440 22-3 prom programming operating modes ................................................................................ 441 23-1 operand identifiers and description methods ...................................................................... 450
users manual u10105ej4v1um00 [memo]
1 users manual u10105ej4v1um00 chapter 1 outline ( m pd78064 subseries) 1.1 features l l on-chip high-capacity rom and ram note the capacities of internal prom and internal high-speed ram can be changed by means of the memory size switching register. l l instruction execution time changeable from high speed (0.4 m s: in main system clock 5.0 mhz operation) to ultra- low speed (122 m s: in subsystem clock 32.768 khz operation) l l instruction set suited to system control ? bit manipulation possible in all address spaces ? multiply and divide instructions l l fifty-seven i/o ports (including alternative function pins for segment signal output) l l lcd controller / driver ? segment signal output: max. 40 ? common signal output: max. 4 ? bias: 1/2, 1/3 bias switching possible ? power supply voltage: v dd = 2.0 to 6.0 v (static display mode) v dd = 2.5 to 6.0 v (1/3 bias method) v dd = 2.7 to 6.0 v (1/2 bias method) l l 8-bit resolution a/d converter: 8 channels l l serial interface: 2 channels ? 3-wire/sbi/2-wire mode: 1 channel ? 3-wire/uart mode: 1 channel l l timer: 5 channels ? 16-bit timer/event counter: 1 channel ? 8-bit timer/event counter: 2 channels ? watch timer: 1 channel ? watchdog timer: 1 channel l l twenty vectored interrupts l l two test inputs l l two types of on-chip clock oscillators (main system clock and subsystem clock) l l power supply voltage: v dd = 2.0 to 6.0 v m pd78062 m pd78063 m pd78064 m pd78p064 program memory (rom) data memory internal high-speed ram lcd ram 40 x 4 bytes part number type 16 kbytes 24 kbytes 32 kbytes 32 kbytes ( note ) 512 bytes 1024 bytes 1024 bytes ( note )
2 chapter 1 outline ( m pd78064 subseries) users manual u10105ej4v1um00 1.2 applications cellular phones, cd players, cameras, etc. 1.3 ordering information part number package internal rom m pd78062gc- -7ea 100-pin plastic qfp (fine pitch) (14 x 14 mm) mask rom m pd78062gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd78063gc- -7ea 100-pin plastic qfp (fine pitch) (14 x 14 mm) mask rom m pd78063gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd78064gc- -7ea 100-pin plastic qfp (fine pitch) (14 x 14 mm) mask rom m pd78064gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd78p064gc-7ea 100-pin plastic qfp (fine pitch) (14 x 14 mm) one-time prom m pd78p064gf-3ba 100-pin plastic qfp (14 x 20 mm) one-time prom m pd78p064kl-t * 100-pin ceramic wqfn eprom * : under development remark indicates rom code suffix.
3 chapter 1 outline ( m pd78064 subseries) users manual u10105ej4v1um00 1.4 pin configuration (top view) (1) normal operating mode 100-pin plastic qfp (fine pitch) (14 x 14 mm) m pd78062gc-xxx-7ea, 78063gc-xxx-7ea, 78064gc-xxx-7ea, 78p064gc-7ea cautions 1. be sure to connect ic (internally connected) pin to v ss directly. 2. connect av dd pin to v dd . 3. connect av ss pin to v ss . remark pin connection in parentheses is intended for the m pd78p064. 75 74 73 72 71 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 70 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 6 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p70/si2/rxd p27/sck0 p26/so0/sb1 p25/si0/sb0 p80/s39 p82/s37 p83/s36 p84/s35 p85/s34 p86/s33 p87/s32 p90/s31 p91/s30 p92/s29 p93/s28 p94/s27 p95/s26 p96/s25 p97/s24 s23 s22 s21 p81/s38 s20 s19 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p17/ani7 av dd av ref p100 p101 v ss p102 p103 p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p37 com0 p16/ani6 com1 com2 p10/ani0 av ss p117 p116 p115 p114 p113 p112 p111 p110 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1/ti01 p00/intp0/ti00 reset xt2 xt1/p07 v dd x1 x2 ic (v pp ) p72/sck2/asck p71/so2/txd com3 bias v lc0 v lc1 v lc2 v ss s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18
4 chapter 1 outline ( m pd78064 subseries) users manual u10105ej4v1um00 100-pin plastic qfp (14 x 20 mm) m pd78062gf-xxx-3ba, 78063gf-xxx-3ba, 78064gf-xxx-3ba, 78p064gf-3ba 100-pin ceramic wqfn m pd78p064kl-t* * : under development cautions 1. be sure to connect ic (internally connected) pin to v ss directly. 2. connect av dd pin to v dd . 3. connect av ss pin to v ss . remark pin connection in parentheses is intended for the m pd78p064. 31 32 35 36 33 34 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 96 95 98 97 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p26/so0/sb1 p27/sck0 p70/si2/rxd p72/sck2/asck ic (v pp ) x2 x1 v dd xt1/p07 xt2 reset p00/intp0/ti00 p02/intp2 p03/intp3 p04/intp4 p05/intp5 p110 p111 p112 p113 p114 p115 p116 p117 av ss p10/ani0 p11/ani1 p12/ani2 p01/intp1/ti01 p71/so2/txd p25/si0/sb0 p80/s39 p81/s38 p82/s37 p83/s36 p84/s35 p85/s34 p86/s33 p87/s32 p90/s31 p91/s30 p92/s29 p93/s28 p94/s27 p95/s26 p96/s25 p97/s24 s23 s22 s21 s20 s19 s18 s16 s15 s14 s13 s12 s11 s10 s9 s8 s6 s5 s4 s3 s2 s1 s0 v ss v lc2 v lc1 v lc0 bias com3 com2 com1 com0 s7 s17 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av dd av ref p100 p101 v ss p102 p103 p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p37
5 chapter 1 outline ( m pd78064 subseries) users manual u10105ej4v1um00 p00 to p05, p07 : port 0 asck : asynchronous serial clock p10 to p17 : port 1 pcl : programmable clock p25 to p27 : port 2 buz : buzzer clock p30 to p37 : port 3 s0 to s39 : segment output p70 to p72 : port 7 com0 to com3 : common output p80 to p87 : port 8 v lc0 to v lc2 : lcd power supply p90 to p97 : port 9 bias : lcd power supply bias control p100 to p103 : port 10 x1, x2 : crystal (main system clock) p110 to p117 : port 11 xt1, xt2 : crystal (subsystem clock) intp0 to intp5 : interrupt from peripherals reset : reset ti00, ti01 : timer input ani0 to ani7 : analog input ti1, ti2 : timer input av dd : analog power supply to0 to to2 : timer output av ss : analog ground sb0, sb1 : serial bus av ref : analog reference voltage si0 to si2 : serial input v dd : power supply so0 to so2 : serial output v pp : programming power supply sck0 to sck2 : serial clock v ss : ground rxd : receive data ic : internally connected txd : transmit data
6 chapter 1 outline ( m pd78064 subseries) users manual u10105ej4v1um00 (2) prom programming mode 100-pin plastic qfp (fine pitch) (14 x 14 mm) m pd78p064gc-7ea cautions 1. (l) : connect individually to v ss via a pull-down resistor. 2. v ss : connect to the ground. 3. reset : set to the low level. 4. open : do not connect anything. (l) (l) (l) (l) ce oe a9 reset open v dd pgm v pp open a0 a1 a2 a3 a4 a5 a6 a7 a8 a16 a10 a11 a12 a13 a14 a15 75 74 73 72 71 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 70 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 6 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (l) v dd v ss d0 d1 v ss d2 d3 d4 d5 d6 d7 (l) (l) (l) (l) (l) (l) (l) (l)
7 chapter 1 outline ( m pd78064 subseries) users manual u10105ej4v1um00 100-pin plastic qfp (14 x 20 mm) m pd78p064gf-3ba 100-pin ceramic wqfn m pd78p064kl-t* * : under development cautions 1. (l) : connect individually to v ss via a pull-down resistor. 2. v ss : connect to the ground. 3. reset : set to the low level. 4. open : do not connect anything. a0 to a16 : address bus reset : reset d0 to d7 : data bus v dd : power supply ce : chip enable v pp : programming power supply oe : output enable v ss : ground pgm : program (l) a0 a1 a2 a3 a4 a5 a6 a7 a8 a16 a10 a11 a12 a13 a14 a15 (l) v pp open v dd open reset a9 pgm oe ce v ss v ss v dd d0 d1 d3 d2 d4 d5 d6 d7 31 32 35 36 33 34 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 96 95 98 97 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 (l) (l) (l) (l) (l) (l) (l) (l) (l) (l)
8 chapter 1 outline ( m pd78064 subseries) users manual u10105ej4v1um00 1.5 78k/0 series expansion 78k/0 series products evolution is illustrated below. part numbers in the boxes indicate subseries names. * 100-pin 100-pin 80-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin 100-pin 80-pin 64-pin 78k/0 series 100-pin 80-pin pd78064 pd78064y supports iebus. tm drives lcds. pd780208 pd78044a pd78024 drives vfd (fips ). pd78054 pd78018f pd78078y pd78070ay pd78054y pd78018fy pd78014y performs control. adds timers and enhances external interface based on pd78054. rom-less version of pd78078. adds uart and d/a and enhances i/os based on pd78014. operates at 1.8 v and enhances rom/ram size selection based on pd78014 . adds a/d and 16-bit timer based on pd78002. adds a/d based on pd78002. basic subseries for control applications operates at 1.8 v and has uart. enhances i/o, fip c/d based on pd78044a : max. 53 display outputs adds 6-bit u/d counter based on pd78024 : max. 34 display outputs basic subseries for driving fips : max. 26 display outputs subseries for driving lcds, has uart. adds iebus controller based on pd78054. mass-produced under development y subseries supports i 2 c bus specifications. tm pd78002 pd78083 pd78002y pd78078 pd78070a pd780001 pd78014 pd78098
9 chapter 1 outline ( m pd78064 subseries) users manual u10105ej4v1um00 major differences among these subseries are tabulated below. function rom timer 8-bit 8-bit serial interface i/o v dd external subseries capacity 8-bit 16-bit watch watchdog a/d d/a min extension control m pd78078 32k-60k 4ch 1ch 1ch 1ch 8ch 2ch 3ch(uart:1ch) 88 1.8 v ? m pd78070a 61 2.7 v m pd78054 16k-60k 2ch 69 2.0 v m pd78018f 8k-48k 2ch 53 1.8 v m pd78014 8k-32k 2.7 v m pd780001 8k 1ch 39 m pd78002 8k-16k 1ch 53 ? m pd78083 8ch 1ch (uart:1ch) 33 1.8 v fip m pd780208 32k-40k 2ch 1ch 1ch 1ch 8ch 2ch 74 2.7 v drive m pd78044a 16k-40k 68 m pd78024 24k-32k 54 lcd m pd78064 16k-32k 2ch 1ch 1ch 1ch 8ch 2ch(uart:1ch) 57 2.0 v drive iebus m pd78098 32k-60k 2ch 1ch 1ch 1ch 8ch 2ch 3ch(uart:1ch) 69 2.7 v ? support
10 chapter 1 outline ( m pd78064 subseries) users manual u10105ej4v1um00 1.6 block diagram remarks 1. the internal rom and ram capacities depend on the product. 2. pin connection in parentheses is intended for the m pd78p064. to0/p30 ti00/intp0/p00 ti01/intp1/p01 to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/p25 so0/sb1/p26 sck0/p27 si2/rxd/p70 so2/txd/p71 sck2/asck/p72 av dd av ss av ref ani0/p10- ani7/p17 intp0/p00- intp5/p05 buz/p36 pcl/p35 16-bit timer/ event counter 8-bit timer/ event counter 1 8-bit timer/ event counter 2 watchdog timer watch timer serial interface 0 serial interface 2 a/d converter interrupt control buzzer output clock output control 78k/0 cpu core rom ram v dd v ss ic (v pp ) port 0 port 1 port 2 port 3 port 7 port 8 port 9 port 10 port 11 p00 p01-p05 p07 p10-p17 p25-p27 p30-p37 p70-p72 p80-p87 p90-p97 p100-p103 p110-p117 s0-s23 s24/p97- s31/p90 s32/p87- s39/p80 com0-com3 v lc0 -v lc2 bias f lcd reset x1 x2 xt1/p07 xt2 lcd controller/ driver system control
11 chapter 1 outline ( m pd78064 subseries) users manual u10105ej4v1um00 1.7 outline of function rom mask rom prom 16 kbytes 24 kbytes 32 kbytes 32 kbytes note internal high-speed ram 512 bytes 1024 bytes 1024 bytes note lcd ram 40 x 4 bits general register 8 bits 8 4 banks instruction with main system clock selected 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (@ 5.0 mhz) cycle with subsystem clock selected 122 m s (@ 32.768 khz) instruction set ? 16-bit operation ? multiply/divide (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulate (set, reset, test, and boolean operation) ? bcd adjust, etc. i/o port (including alternative function pins ? total : 57 for segment signal output) ? cmos input : 2 ? cmos i/o : 55 a/d converter 8-bit resolution 8 channels lcd controller / driver ? segment signal output: max. 40 ? common signal output: max. 4 ? bias: 1/2, 1/3 bias switching possible serial interface ? 3-wire/sbi/2-wire mode selection possible : 1 channel ? 3-wire mode / uart mode selection possible : 1 channel timer ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel timer output three outputs: (14-bit pwm output enable: 1) clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (@ 5.0 mhz with main system clock) 32.768 khz (@ 32.768 khz with subsystem clock) buzzer output 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (@ 5.0 mhz with main system clock) note the capacities of the internal prom and the internal high-speed ram can be changed using the memory size switching register. item part number internal memory m pd78062 m pd78063 m pd78064 m pd78p064
12 chapter 1 outline ( m pd78064 subseries) users manual u10105ej4v1um00 item part number m pd78062 m pd78063 m pd78064 m pd78p064 * maskable interrupt internal: 12 vectored external: 6 interrupt non-maskable interrupt internal: 1 software interrupt internal: 1 test input internal: 1 external: 1 power supply voltage v dd = 2.0 to 6.0 v operating ambient temperature t a = C40 to +85 c package ? 100-pin plastic qfp (fine pitch) (14 x 14 mm) ? 100-pin plastic qfp (14 20 mm) ? 100-pin ceramic wqfn note ( m pd78p064 only) note under development 1.8 mask options the mask rom versions ( m pd78062, 78063, 78064) provide split resistor mask options. by specifying this mask options at the time of ordering, split registers which enable to generate lcd drive voltage suited to each bias method type can be incorporated. using this mask option reduces the number of components to add to the device, resulting in board space saving. the mask options provided in the m pd78064 subseries are shown in table 1-1. table 1-1. mask options of mask rom versions pin names mask options v lc0 -v lc2 split register can be incorporated.
13 users manual u10105ej4v1um00 chapter 2 outline ( m pd78064y subseries) 2.1 features l l on-chip high-capacity rom and ram note the capacities of internal prom and internal high-speed ram can be changed by means of the memory size switching register. l l instruction execution time changeable from high speed (0.4 m s: in main system clock 5.0 mhz operation) to ultra- low speed (122 m s: in subsystem clock 32.768 khz operation) l l instruction set suited to system control ? bit manipulation possible in all address spaces ? multiply and divide instructions l l fifty-seven i/o ports (including alternative function pins for segment signal output) l l lcd controller / driver ? segment signal output: max. 40 ? common signal output: max. 4 ? bias: 1/2, 1/3 bias switching possible ? power supply voltage: v dd = 2.0 to 6.0 v (static display mode) v dd = 2.5 to 6.0 v (1/3 bias method) v dd = 2.7 to 6.0 v (1/2 bias method) l l 8-bit resolution a/d converter: 8 channels l l serial interface: 2 channels ? 3-wire//2-wire/i 2 c bus mode: 1 channel ? 3-wire/uart mode: 1 channel l l timer: 5 channels ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel l l twenty vectored interrupts l l two test inputs l l two types of on-chip clock oscillators (main system clock and subsystem clock) l l power supply voltage: v dd = 2.0 to 6.0 v m pd78062y m pd78063y m pd78064y m pd78p064y program memory (rom) data memory internal high-speed ram lcd ram 40 x 4 bytes part number type 16 kbytes 24 kbytes 32 kbytes 32 kbytes ( note ) 512 bytes 1024 bytes 1024 bytes ( note ) *
14 chapter 2 outline ( m pd78064y subseries) users manual u10105ej4v1um00 2.2 applications cellular phones, cd players, cameras, audio equipment, etc. 2.3 ordering information part number package internal rom m pd78062ygc- -7ea 100-pin plastic qfp (fine pitch) (14 x 14 mm) mask rom m pd78062ygf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd78063ygc- -7ea 100-pin plastic qfp (fine pitch) (14 x 14 mm) mask rom m pd78063ygf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd78064ygc- -7ea 100-pin plastic qfp (fine pitch) (14 x 14 mm) mask rom m pd78064ygf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd78p064ygc-7ea * 100-pin plastic qfp (fine pitch) (14 x 14 mm) one-time prom m pd78p064ygf-3ba * 100-pin plastic qfp (14 x 20 mm) one-time prom m pd78p064ykl-t * 100-pin ceramic wqfn eprom * : under development remark indicates rom code suffix.
15 chapter 2 outline ( m pd78064y subseries) users manual u10105ej4v1um00 2.4 pin configuration (top view) (1) normal operating mode 100-pin plastic qfp (fine pitch) (14 x 14 mm) m pd78062ygc-xxx-7ea, 78063ygc-xxx-7ea, 78064ygc-xxx-7ea, 78p064ygc-7ea * * : under development cautions 1. be sure to connect ic (internally connected) pin to v ss directly. 2. connect av dd pin to v dd . 3. connect av ss pin to v ss . remark pin connection in parentheses is intended for the m pd78p064y. 75 74 73 72 71 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 70 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 6 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p70/si2/rxd p27/sck0/scl p26/so0/sb1/sda1 p25/si0/sb0/sda0 p80/s39 p82/s37 p83/s36 p84/s35 p85/s34 p86/s33 p87/s32 p90/s31 p91/s30 p92/s29 p93/s28 p94/s27 p95/s26 p96/s25 p97/s24 s23 s22 s21 p81/s38 s20 s19 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p17/ani7 av dd av ref p100 p101 v ss p102 p103 p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p37 com0 p16/ani6 com1 com2 p10/ani0 av ss p117 p116 p115 p114 p113 p112 p111 p110 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1/ti01 p00/intp0/ti00 reset xt2 xt1/p07 v dd x1 x2 ic (v pp ) p72/sck2/asck p71/so2/txd com3 bias v lc0 v lc1 v lc2 v ss s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18
16 chapter 2 outline ( m pd78064y subseries) users manual u10105ej4v1um00 100-pin plastic qfp (14 x 20 mm) m pd78062ygf-xxx-3ba, 78063ygf-xxx-3ba, 78064ygf-xxx-3ba, 78p064ygf-3ba* 100-pin ceramic wqfn m pd78p064ykl-t* * : under development cautions 1. be sure to connect ic (internally connected) pin to v ss directly. 2. connect av dd pin to v dd . 3. connect av ss pin to v ss . remark pin connection in parentheses is intended for the m pd78p064y. 31 32 35 36 33 34 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 96 95 98 97 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p26/so0/sb1/sda1 p27/sck0/scl p70/si2/rxd p72/sck2/asck ic (v pp ) x2 x1 v dd xt1/p07 xt2 reset p00/intp0/ti00 p02/intp2 p03/intp3 p04/intp4 p05/intp5 p110 p111 p112 p113 p114 p115 p116 p117 av ss p10/ani0 p11/ani1 p12/ani2 p01/intp1/ti01 p71/so2/txd p25/si0/sb0/sda0 p80/s39 p81/s38 p82/s37 p83/s36 p84/s35 p85/s34 p86/s33 p87/s32 p90/s31 p91/s30 p92/s29 p93/s28 p94/s27 p95/s26 p96/s25 p97/s24 s23 s22 s21 s20 s19 s18 s16 s15 s14 s13 s12 s11 s10 s9 s8 s6 s5 s4 s3 s2 s1 s0 v ss v lc2 v lc1 v lc0 bias com3 com2 com1 com0 s7 s17 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av dd av ref p100 p101 v ss p102 p103 p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p37
17 chapter 2 outline ( m pd78064y subseries) users manual u10105ej4v1um00 p00 to p05, p07 : port 0 txd : transmit data p10 to p17 : port 1 asck : asynchronous serial clock p25 to p27 : port 2 pcl : programmable clock p30 to p37 : port 3 buz : buzzer clock p70 to p72 : port 7 s0 to s39 : segment output p80 to p87 : port 8 com0 to com3 : common output p90 to p97 : port 9 v lc0 to v lc2 : lcd power supply p100 to p103 : port 10 bias : lcd power supply bias control p110 to p117 : port 11 x1, x2 : crystal (main system clock) intp0 to intp5 : interrupt from peripherals xt1, xt2 : crystal (subsystem clock) ti00, ti01 : timer input reset : reset ti1, ti2 : timer input ani0 to ani7 : analog input to0 to to2 : timer output av dd : analog power supply sb0, sb1 : serial bus av ss : analog ground si0 to si2 : serial input av ref : analog reference voltage so0 to so2 : serial output v dd : power supply sck0 to sck2 : serial clock v pp : programming power supply sda0, sda1 : serial data v ss : ground scl : serial clock ic : internally connected rxd : receive data
18 chapter 2 outline ( m pd78064y subseries) users manual u10105ej4v1um00 (2) prom programming mode 100-pin plastic qfp (fine pitch) (14 x 14 mm) m pd78p064ygc-7ea* * : under development cautions 1. (l) : connect individually to v ss via a pull-down resistor. 2. v ss : connect to the ground. 3. reset : set to the low level. 4. open : do not connect anything. (l) (l) (l) (l) ce oe a9 reset open v dd pgm v pp open a0 a1 a2 a3 a4 a5 a6 a7 a8 a16 a10 a11 a12 a13 a14 a15 75 74 73 72 71 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 70 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 6 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (l) v dd v ss d0 d1 v ss d2 d3 d4 d5 d6 d7 (l) (l) (l) (l) (l) (l) (l) (l)
19 chapter 2 outline ( m pd78064y subseries) users manual u10105ej4v1um00 100-pin plastic qfp (14 x 20 mm) m pd78p064ygf-3ba* 100-pin ceramic wqfn m pd78p064ykl-t* * : under development cautions 1. (l) : connect individually to v ss via a pull-down resistor. 2. v ss : connect to the ground. 3. reset : set to the low level. 4. open : do not connect anything. a0 to a16 : address bus reset : reset d0 to d7 : data bus v dd : power supply ce : chip enable v pp : programming power supply oe : output enable v ss : ground pgm : program (l) a0 a1 a2 a3 a4 a5 a6 a7 a8 a16 a10 a11 a12 a13 a14 a15 (l) v pp open v dd open reset a9 pgm oe ce v ss v ss v dd d0 d1 d3 d2 d4 d5 d6 d7 31 32 35 36 33 34 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 96 95 98 97 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 (l) (l) (l) (l) (l) (l) (l) (l) (l) (l)
20 chapter 2 outline ( m pd78064y subseries) users manual u10105ej4v1um00 2.5 78k/0 series expansion 78k/0 series products evolution is illustrated below. part numbers in the boxes indicates subseries names. 100-pin 100-pin 80-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin 100-pin 80-pin 64-pin 78k/0 series 100-pin 80-pin pd78064 pd78064y supports iebus. tm drives lcds. pd780208 pd78044a pd78024 drives vfd (fips ). pd78054 pd78018f pd78078y pd78070ay pd78054y pd78018fy pd78014y performs control. adds timers and enhances external interface based on pd78054. rom-less version of pd78078. adds uart and d/a and enhances i/os based on pd78014. operates at 1.8 v and enhances rom/ram size selection based on pd78014 . adds a/d and 16-bit timer based on pd78002. adds a/d based on pd78002. basic subseries for control applications operates at 1.8 v and has uart. enhances i/o, fip c/d based on pd78044a : max. 53 display outputs adds 6-bit u/d counter based on pd78024 : max. 34 display outputs basic subseries for driving fips : max. 26 display outputs subseries for driving lcds, has uart. adds iebus controller based on pd78054. mass-produced under development y subseries supports i 2 c bus specifications. tm pd78002 pd78083 pd78002y pd78078 pd78070a pd780001 pd78014 pd78098 *
21 chapter 2 outline ( m pd78064y subseries) users manual u10105ej4v1um00 major differences among these subseries are tabulated below. function rom timer 8-bit 8-bit serial interface i/o v dd external subseries capacity 8-bit 16-bit watch watchdog a/d d/a min extension control m pd78078 32k-60k 4ch 1ch 1ch 1ch 8ch 2ch 3ch(uart:1ch) 88 1.8 v ? m pd78070a 61 2.7 v m pd78054 16k-60k 2ch 69 2.0 v m pd78018f 8k-48k 2ch 53 1.8 v m pd78014 8k-32k 2.7 v m pd780001 8k 1ch 39 m pd78002 8k-16k 1ch 53 ? m pd78083 8ch 1ch (uart:1ch) 33 1.8 v fip m pd780208 32k-40k 2ch 1ch 1ch 1ch 8ch 2ch 74 2.7 v drive m pd78044a 16k-40k 68 m pd78024 24k-32k 54 lcd m pd78064 16k-32k 2ch 1ch 1ch 1ch 8ch 2ch(uart:1ch) 57 2.0 v drive iebus m pd78098 32k-60k 2ch 1ch 1ch 1ch 8ch 2ch 3ch(uart:1ch) 69 2.7 v ? support
22 chapter 2 outline ( m pd78064y subseries) users manual u10105ej4v1um00 2.6 block diagram remarks 1. the internal rom and ram capacities depend on the product. 2. pin connection in parentheses is intended for the m pd78p064. to0/p30 ti00/intp0/p00 ti01/intp1/p01 to1/p31 ti1/p33 to2/p32 ti2/p34 sda0/si0/sb0/p25 sda1/so0/sb1/p26 scl/sck0/p27 si2/rxd/p70 so2/txd/p71 sck2/asck/p72 av dd av ss av ref ani0/p10- ani7/p17 intp0/p00- intp5/p05 buz/p36 pcl/p35 16-bit timer/ event counter 8-bit timer/ event counter 1 8-bit timer/ event counter 2 watchdog timer watch timer serial interface 0 serial interface 2 a/d converter interrupt control buzzer output clock output control 78k/0 cpu core rom ram v dd v ss ic (v pp ) port 0 port 1 port 2 port 3 port 7 port 8 port 9 port 10 port 11 p00 p01-p05 p07 p10-p17 p25-p27 p30-p37 p70-p72 p80-p87 p90-p97 p100-p103 p110-p117 s0-s23 s24/p97- s31/p90 s32/p87- s39/p80 com0-com3 v lc0 -v lc2 bias f lcd reset x1 x2 xt1/p07 xt2 lcd controller/ driver system control
23 chapter 2 outline ( m pd78064y subseries) users manual u10105ej4v1um00 2.7 outline of function rom mask rom prom 16 kbytes 24 kbytes 32 kbytes 32 kbytes note2 internal high-speed ram 512 bytes 1024 bytes 1024 bytes note2 lcd ram 40 x 4 bits general register 8 bits 8 4 banks instruction with main system clock selected 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (@ 5.0 mhz) cycle with subsystem clock selected 122 m s (@ 32.768 khz) instruction set ? 16-bit operation ? multiply/divide (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulate (set, reset, test, and boolean operation) ? bcd adjust, etc. i/o port (including alternative function pins ? total : 57 for segment signal output) ? cmos input : 2 ? cmos i/o : 55 a/d converter 8-bit resolution 8 channels lcd controller / driver ? segment signal output: max. 40 ? common signal output: max. 4 ? bias: 1/2, 1/3 bias switching possible serial interface ? 3-wire/2-wire/i 2 c bus mode selection possible: 1 channel ? 3-wire mode / uart mode selection possible: 1 channel timer ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel timer output three outputs: (14-bit pwm output enable: 1) clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (@ 5.0 mhz with main system clock) 32.768 khz (@ 32.768 khz with subsystem clock) buzzer output 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (@ 5.0 mhz with main system clock) notes 1. under development 2. the capacities of the internal prom and the internal high-speed ram can be changed using the memory switching register. item part number internal memory m pd78062y m pd78063y m pd78064y m pd78p064y note1
24 chapter 2 outline ( m pd78064y subseries) users manual u10105ej4v1um00 maskable interrupt internal: 12 vectored external: 6 interrupt non-maskable interrupt internal: 1 software interrupt internal: 1 test input internal: 1 external: 1 power supply voltage v dd = 2.0 to 6.0 v operating ambient temperature t a = C40 to +85 c package ? 100-pin plastic qfp (fine pitch) (14 x 14 mm) ? 100-pin plastic qfp (14 20 mm) ? 100-pin ceramic wqfn ( m pd78p064y only) note under development 2.8 mask options the mask rom versions ( m pd78062y, 78063y, 78064y) provide split resistor mask options. by specifying this mask options at the time of ordering, split registers which enable to generate lcd drive voltage suited to each bias method type can be incorporated. using this mask option reduces the number of components to add to the device, resulting in board space saving. the mask options provided in the m pd78064y subseries are shown in table 2-1. table 2-1. mask options of mask rom versions pin names mask options v lc0 -v lc2 split register can be incorporated. item part number m pd78062y m pd78063y m pd78064y m pd78p064y note
25 users manual u10105ej4v1um00 input/ output input chapter 3 pin function ( m pd78064 subseries) 3.1 pin function list 3.1.1 normal operating mode pins (1) port pins (1/2) p25 p27 p26 pin name input/output function after reset alternative function p00 input port 0. input only input intp0/ti00 p01 input/ 7-bit input/output port. input/output mode can be specified input intp1/ti01 p02 output bit-wise. intp2 p03 if used as an input port, a pull-up intp3 p04 resistor can be connected by intp4 p05 software. intp5 p07 note1 input input only input xt1 p10 to p17 port 1. input ani0 to ani7 8-bit input/output port. input/output mode can be specified bit-wise. if used as input port, a pull-up resistor can be connected by software note2 . input/ port 2. input output/ 3-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. p30 input/ port 3. to0 p31 output 8-bit input/output port. to1 p32 input/output mode can be specified bit-wise. to2 p33 if used as an input port, a pull-up resistor can be connected by software. ti1 p34 ti2 p35 pcl p36 buz p37 notes 1. when the p07/xt1 pin is used as an input port, set the bit 6 (frc) of the processor clock control register to 1 (do not use the feedback resistor internal to the subsystem clock oscillator). 2. when pins p10/ani0 to p17/ani7 are used as an analog input of the a/d converter, the pull-up resistor is automatically disabled. si0/sb0 so0/sb1 sck0
26 chapter 3 pin function ( m pd78064 subseries) users manual u10105ej4v1um00 (1) port pins (2/2) pin name input/output function after reset alternative function input/ port 7. input output 3-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. p80 to p87 input/ port 8. input s39 to s32 output 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. i/o port / segment signal output can be specified in 2-bit units by lcd control register. input/ port 9. output 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. i/o port / segment signal output can be specified in 2-bit units by lcd control register. port 10. input 4-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. a resistor can be connected. led can be driven directly. p110 to 117 input/ port 11. input output 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. falling edge can be detected. p70 si2/rxd p71 so2/txd p72 sck2/asck p90 to p97 input s31 to s24 p100 to p103 input/ output
27 chapter 3 pin function ( m pd78064 subseries) users manual u10105ej4v1um00 (2) pins other than port pins (1/2) pin name input/output function after reset alternative function intp0 input external interrupt inputs with specifiable valid edges (rising edge, falling input p00/ti00 intp1 edge, both rising and falling edges). p01/ti01 intp2 p02 intp3 p03 intp4 p04 intp5 p05 si0 input serial interface serial data input input p25/sb0 si2 p70/rxd so0 output serial interface serial data output input p26/sb1 so2 p71/txd sb0 input/ serial interface serial data input/output input p25/si0 sb1 output p26/so0 sck0 input/ serial interface serial clock input/output input p27 sck2 output p72/asck rxd input asynchronous serial interface serial data input input p70/si2 txd output asynchronous serial interface serial data output input p71/so2 asck input asynchronous serial interface serial clock input input p72/sck2 ti00 input external count clock input to 16-bit timer (tm0) input p00/intp0 ti01 capture trigger signal input to capture register (cr00) p01/intp1 ti1 external count clock input to 8-bit timer (tm1) p33 ti2 external count clock input to 8-bit timer (tm2) p34 to0 output 16-bit timer output (also used for 14-bit pwm output) input p30 to1 8-bit timer output p31 to2 p32 pcl output clock output (for main system clock and subsystem clock trimming) input p35 buz output buzzer output input p36 s0 to s23 output segment signal output of lcd controller/driver output s24 to s31 input p97 to p90 s32 to s39 p87 to p80 com0-com3 output common signal output of lcd controller/driver output v lc0 to v lc2 lcd drive voltage (mask rom versions can incorporate dividing resistor (mask option.)) bias power supply for lcd drive ani0 to ani7 input a/d converter analog input input p10 to p17 av ref input d/a converter analog output av dd a/d converter reference voltage input
28 chapter 3 pin function ( m pd78064 subseries) users manual u10105ej4v1um00 (2) pins other than port pins (2/2) pin name input/output function after reset alternative function av ss a/d converter ground potential. connect to v ss . reset input system reset input x1 input crystal connection for main system clock oscillation x2 xt1 input crystal connection for subsystem clock oscillation input p07 xt2 v dd positive power supply v pp high-voltage application for program write/verify. connect directly to v ss in normal operating mode. v ss ground potential ic internal connection. connect directly to v ss. 3.1.2 prom programming mode pins ( m pd78p064 only) pin name input/output function reset input prom programming mode setting. when +5 v or +12.5 v is applied to the v pp pin or a low level voltage is applied to the reset pin, the prom programming mode is set. v pp input high-voltage application for prom programming mode setting and program write/verify. a0 to a16 input address bus d0 to d7 input/output data bus ce input prom enable input/program pulse input oe input read strobe input to prom pgm input program/program inhibit input in prom programming mode v dd positive power supply v ss ground potential *
29 chapter 3 pin function ( m pd78064 subseries) users manual u10105ej4v1um00 3.2 description of pin functions 3.2.1 p00 to p05, p07 (port 0) these are 7-bit input/output ports. besides serving as input/output ports, they function as an external interrupt input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem clock oscillation. the following operating modes can be specified bit-wise. (1) port mode p00 and p07 function as input-only ports and p01 to p05 function as input/output ports. p01 to p05 can be specified for input or output ports bit-wise with a port mode register 0. when they are used as input ports, pull-up resistors can be connected to them by defining the pull-up resistor option register l. (2) control mode in this mode, these ports function as an external interrupt input, an external count clock input to the timer, and crystal connection for subsystem clock oscillation. (a) intp0 to intp5 intp0 to intp5 are external interrupt input pins which can specify valid edges (rising edge, falling edge, and both rising and falling edges). intp0 or intp1 becomes a 16-bit timer/event counter capture trigger signal input pin with a valid edge input. (b) ti00 pin for external count clock input to 16-bit timer/event counter (c) ti01 pin for capture trigger signal input to capture register (cr00) of 16-bit timer/event counter (d) xt1 crystal connect pin for subsystem clock oscillation
30 chapter 3 pin function ( m pd78064 subseries) users manual u10105ej4v1um00 3.2.2 p10 to p17 (port 1) these are 8-bit input/output ports. besides serving as input/output ports, they function as an a/d converter analog input. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with a port mode register 1. if used as input ports, pull-up resistors can be connected to these ports by defining the pull-up resistor option register l. (2) control mode these ports function as a/d converter analog input pins (ani0-ani7). the pull-up resistor is automatically disabled when the pins specified for analog input. 3.2.3 p25 to p27 (port 2) these are 3-bit input/output ports. besides serving as input/output ports, they function as data input/output to/ from the serial interface and clock input/output. the following operating modes can be specified bit-wise. (1) port mode these ports function as 3-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 2. when they are used as input ports, pull-up resistors can be connected to them by defining the pull-up resistor option register l. (2) control mode these ports function as serial interface data input/output and clock input/output. (a) si0, so0 serial interface serial data input/output pins (b) sck0 serial interface serial clock input/output pins (c) sb0 and sb1 nec standard serial bus interface input/output pins caution when this port is used as a serial interface, the i/o and output latches must be set according to the function the user requires. for the setting, refer to figure 15-4 serial operation mode register 0 format.
31 chapter 3 pin function ( m pd78064 subseries) users manual u10105ej4v1um00 3.2.4 p30 to p37 (port 3) these are 8-bit input/output ports. beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 3. when they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register l. (2) control mode these ports function as timer input/output, clock output, and buzzer output. (a) ti1 and ti2 pin for external clock input to the 8-bit timer/event counter. (b) to0 to to2 timer output pins. (c) pcl clock output pin. (d) buz buzzer output pin.
32 chapter 3 pin function ( m pd78064 subseries) users manual u10105ej4v1um00 3.2.5 p70 to p72 (port 7) these are 3-bit input/output ports. beside serving as input/output ports, they function as serial interface data input/ output, clock input/output. the following operating modes can be specified bit-wise. (1) port mode these ports function as 3-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 7. when they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register l. (2) control mode these ports function as serial interface data input/output and clock input/output. (a) si2, so2 serial interface serial data input/output pins (b) sck2 serial interface serial clock input/output pin. (c) rxd, txd asynchronous serial interface serial data input/output pins. (d) asck asynchronous serial interface serial clock input pin. caution when this port is used as a serial interface, the i/o and output latches must be set according to the function the user requires. for the setting, see the operation mode setting list in table 17-2 serial interface channel 2. *
33 chapter 3 pin function ( m pd78064 subseries) users manual u10105ej4v1um00 3.2.6 p80-p87 (port 8) these are 8-bit input/output ports. beside serving as input/output ports, they function as segment signal output of lcd controller/driver. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input/output ports with port mode register 8. when they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register h. (2) control mode these ports function as segment signal output pins (s32 to s39) of lcd controller/driver. 3.2.7 p90-p97 (port 9) these are 8-bit input/output ports. beside serving as input/output ports, they function as segment signal output of lcd controller/driver. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input/output ports with port mode register 9. when they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register h. (2) control mode these ports function as segment signal/output pins (s24 to s31) of lcd controller/driver. 3.2.8 p100-p103 (port 10) these ports function as 4-bit input/output ports. they can be specified bit-wise as input/output ports with port mode register 10. when they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register h. led can be driven directly. 3.2.9 p110-p117 (port 11) these ports function as 8-bit input/output ports. they can be specified bit-wise as input/output ports with port mode register 11. when they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register h. test input flag (krif) can be set to 1 by detecting falling edges.
34 chapter 3 pin function ( m pd78064 subseries) users manual u10105ej4v1um00 3.2.10 com0 to com3 these are lcd controller/driver common signal output pins. they output common signals under either of the following conditions: C when the static mode is selected (com0 to com3 outputs) C when 2-time-division (com0, com1 outputs) or 3-time-division (com0 to com2 outputs) operation is performed in 1/2 bias mode C when 3-time-division (com0 to com2 outputs) or 4-time-division (com0 to com3 outputs) operation is performed in 1/3 bias mode 3.2.11 v lc0 -v lc2 these are lcd-driving voltage pins. the mask rom versions can have split resistors by mask option so that lcd driving voltage can be supplied inside the v lc0 -v lc2 pins according to the required bias without connecting external split resistors. 3.2.12 bias these are lcd driving power supply pins. they should be connected to the v lc0 pin to realize user-desired lcd drive voltages to change resistance division ratios, or should be connected to external resistors together with the v lc0 -v lc2 pins and v ss pin to fine-adjust the lcd-driving power voltage. 3.2.13 av ref this pin inputs the reference voltage for the on-chip a/d converter. when not using the a/d converter,connect this pin to the v ss line. 3.2.14 av dd this pin supplies analog voltage for the on-chip a/d converter. even when not using the a/d converter, always use this pin at the same voltage as v dd . 3.2.15 av ss this is a ground voltage pin of a/d converter. always use the same voltage as that of the v ss pin even when a/d converter is not used. 3.2.16 reset this is a low-level active system reset input pin. 3.2.17 x1 and x2 crystal resonator connect pins for main system clock oscillation. for external clock supply, input it to x1 and its inverted signal to x2. 3.2.18 xt1 and xt2 crystal resonator connect pins for subsystem clock oscillation. for external clock supply, input it to xt1 and its inverted signal to xt2.
35 chapter 3 pin function ( m pd78064 subseries) users manual u10105ej4v1um00 3.2.19 v dd positive power supply pin 3.2.20 v ss ground potential pin 3.2.21 v pp ( m pd78p064 only) high-voltage apply pin for prom programming mode setting and program write/verify. connect directly to v ss in normal operating mode. 3.2.22 ic (mask rom version only) the ic (internally connected) pin is provided to set the test mode to check the m pd78064 subseries at delivery. connect it directly to the v ss with the shortest possible wire in the normal operating mode. when a voltage difference is produced between the ic pin and v ss pin because the wiring between those two pins is too long or an external noise is input to the ic pin, the user's program may not run normally. l l connect ic pins to v ss pins directly. v ss ic as short as possible
36 chapter 3 pin function ( m pd78064 subseries) users manual u10105ej4v1um00 input/output circuit type p00/intp0/ti00 2 input connect to v ss . p01/intp1/ti01 p02/intp2 p03/intp3 p04/intp4 p05/intp5 p07/xt1 16 input connect to v dd . p10/ani0 to p17/ani7 11 input/output p25/si0/sb0 10-a p26/so0/sb1 p27/sck0 p30/to0 5-a p31/to1 p32/to2 p33/ti1 8-a p34/ti2 p35/pcl 5-a p36/buz p37 p70/si2/rxd 8-a p71/so2/txd 5-a p72/sck2/asck 8-a p80/s39-p87/s32 17-a p90/s31-p97/s24 p100-p103 5-a p110-p117 8-a connect to v ss . s0-s23 17 output open com0-com3 18 v lc0 -v lc2 bias reset 2 input xt2 16 open pin name input/output recommended connection of unused pins 3.3 input/output circuits and recommended connection of unused pins table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. refer to figure 3-1 for the configuration of the input/output circuit of each type. table 3-1. pin input/output circuit types (1/2) 8-a input/output connect independently via a resistor to v ss. * * connect independently via a resistor to v dd or v ss .
37 chapter 3 pin function ( m pd78064 subseries) users manual u10105ej4v1um00 pin name input/output recommended connection of unused pins table 3-1. pin input/output circuit types (2/2) input/output circuit type av ref connect to v ss . av dd connect to v dd . av ss connect to v ss . ic (mask rom version) connect directly to v ss . v pp ( m pd78p064 version) *
38 chapter 3 pin function ( m pd78064 subseries) users manual u10105ej4v1um00 figure 3-1. pin input/output circuit of list (1/2) type 2 schmitt-triggered input with hysteresis characteristics in type 5-a data output disable p-ch in/out v dd n-ch input enable p-ch v dd pullup enable type 10-a type 11 data output disable p-ch in/out v dd n-ch p-ch v dd pullup enable open drain data output disable p-ch in/out v dd n-ch input enable p-ch v dd pullup enable comparator + p-ch n-ch v ref (threshold voltage) type 8-a data output disable p-ch in/out v dd n-ch p-ch v dd pullup enable feedback cut-off p-ch xt1 xt2 type 16
39 chapter 3 pin function ( m pd78064 subseries) users manual u10105ej4v1um00 type 17 type 18 type 17-a v lc0 v lc1 seg data v lc2 p-ch n-ch p-ch n-ch p-ch n-ch out v lc0 v lc1 com data v lc2 p-ch n-ch p-ch n-ch p-ch n-ch out n-ch p-ch v lc0 v lc1 seg data v lc2 p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch input enable output disable data pullup enable v dd p-ch in/out v dd figure 3-1. pin input/output circuit of list (2/2)
40 users manual u10105ej4v1um00 [memo]
41 users manual u10105ej4v1um00 input chapter 4 pin function ( m pd78064y subseries) 4.1 pin function list 4.1.1 normal operating mode pins (1) port pins (1/2) pin name input/output function after reset alternative function p00 input port 0. input only input intp0/ti00 p01 input/ 7-bit input/output port. input/output mode can be specified input intp1/ti01 p02 output bit-wise. intp2 p03 if used as an input port, a pull-up intp3 p04 resistor can be connected by intp4 p05 software. intp5 p07 note1 input input only input xt1 p10 to p17 port 1. input ani0 to ani7 8-bit input/output port. input/output mode can be specified bit-wise. if used as input port, a pull-up resistor can be connected by software note2 . input port 2. input output/ 3-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. p30 input/ port 3. to0 p31 output 8-bit input/output port. to1 p32 input/output mode can be specified bit-wise. to2 p33 if used as an input port, a pull-up resistor can be connected by software. ti1 p34 ti2 p35 pcl p36 buz p37 notes 1. when the p07/xt1 pin is used as an input port, set the bit 6 (frc) of the processor clock control register to 1 (do not use the feedback resistor internal to the subsystem clock oscillator). 2. when pins p10/ani0 to p17/ani7 are used as an analog input of the a/d converter, the pull-up resistor is automatically disabled. p25 p26 p27 si0/sb0/sda0 so0/sb1/sda1 sck0/scl input/ output *
42 chapter 4 pin function ( m pd78064y subseries) users manual u10105ej4v1um00 (1) port pins (2/2) pin name input/output function after reset alternative function port 7. output 3-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. p80 to p87 input/ port 8. input s39 to s32 output 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. i/o port / segment signal output can be specified in 2-bit units by lcd control register. input/ port 9. output 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. i/o port / segment signal output can be specified in 2-bit units by lcd control register. port 10. input 4-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. a resistor can be connected. led can be driven directly. p110 to 117 input/ port 11. input output 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. falling edge can be detected. p70 input/ input si2/rxd p71 so2/txd p72 sck2/asck p90 to p97 input s31 to s24 p100 to p103 input/ output
43 chapter 4 pin function ( m pd78064y subseries) users manual u10105ej4v1um00 (2) pins other than port pins (1/2) pin name input/output function after reset alternative function intp0 input external interrupt inputs with specifiable valid edges (rising edge, falling input p00/ti00 intp1 edge, both rising and falling edges). p01/ti01 intp2 p02 intp3 p03 intp4 p04 intp5 p05 si0 input serial interface serial data input input p25/sb0/sda0 si2 p70/rxd so0 output serial interface serial data output input p26/sb1/sda1 so2 p71/txd sb0 input/ serial interface serial data input/output input p25/si0/sda0 sb1 output p26/so0/sda1 sda0 p25/si0/sb0 sda1 p26/so0/sb1 sck0 input/ serial interface serial clock input/output input p27/scl sck2 output p72/asck scl p27/sck0 rxd input asynchronous serial interface serial data input input p70/si2 txd output asynchronous serial interface serial data output input p71/so2 asck input asynchronous serial interface serial clock input input p72/sck2 ti00 input external count clock input to 16-bit timer (tm0) input p00/intp0 ti01 capture trigger signal input to capture register (cr00) p01/intp1 ti1 external count clock input to 8-bit timer (tm1) p33 ti2 external count clock input to 8-bit timer (tm2) p34 to0 output 16-bit timer output (also used for 14-bit pwm output) input p30 to1 8-bit timer output p31 to2 p32 pcl output clock output (for main system clock and subsystem clock trimming) input p35 buz output buzzer output input p36 s0 to s23 output segment signal output of lcd controller/driver output s24 to s31 input p97 to p90 s32 to s39 p87 to p80 com0 to com3 output common signal output of lcd controller/driver output v lc0 to v lc2 lcd drive voltage (mask rom versions can incorporate dividing resistor (mask option).) bias power supply for lcd drive ani0 to ani7 input a/d converter analog input input p10 to p17 av ref input a/d converter analog output av dd a/d converter reference voltage input
44 chapter 4 pin function ( m pd78064y subseries) users manual u10105ej4v1um00 (2) pins other than port pins (2/2) pin name input/output function after reset alternative function av ss a/d converter ground potential. connect to v ss . reset input system reset input x1 input crystal connection for main system clock oscillation x2 xt1 input crystal connection for subsystem clock oscillation input p07 xt2 v dd positive power supply v pp high-voltage application for program write/verify. connect directly to v ss in normal operating mode. v ss ground potential ic internal connection. connect directly to v ss. 4.1.2 prom programming mode pins ( m pd78p064y only) pin name input/output function reset input prom programming mode setting. when +5 v or +12.5 v is applied to the v pp pin or a low level voltage is applied to the reset pin, the prom programming mode is set. v pp input high-voltage application for prom programming mode setting and program write/verify. a0 to a16 input address bus d0 to d7 input/output data bus ce input prom enable input/program pulse input oe input read strobe input to prom pgm input program/program inhibit input in prom programming mode v dd positive power supply v ss ground potential
45 chapter 4 pin function ( m pd78064y subseries) users manual u10105ej4v1um00 4.2 description of pin functions 4.2.1 p00 to p05, p07 (port 0) these are 7-bit input/output ports. besides serving as input/output ports, they function as an external interrupt input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem clock oscillation. the following operating modes can be specified bit-wise. (1) port mode p00 and p07 function as input-only ports and p01 to p05 function as input/output ports. p01 to p05 can be specified for input or output ports bit-wise with a port mode register 0. when they are used as input ports, pull-up resistors can be connected to them by defining the pull-up resistor option register l. (2) control mode in this mode, these ports function as an external interrupt input, an external count clock input to the timer, and crystal connection for subsystem clock oscillation. (a) intp0 to intp5 intp0 to intp5 are external interrupt input pins which can specify valid edges (rising edge, falling edge, and both rising and falling edges). intp0 or intp1 becomes a 16-bit timer/event counter capture trigger signal input pin with a valid edge input. (b) ti00 pin for external count clock input to 16-bit timer/event counter (c) ti01 pin for capture trigger signal input to capture register (cr00) of 16-bit timer/event counter (d) xt1 crystal connect pin for subsystem clock oscillation
46 chapter 4 pin function ( m pd78064y subseries) users manual u10105ej4v1um00 4.2.2 p10 to p17 (port 1) these are 8-bit input/output ports. besides serving as input/output ports, they function as an a/d converter analog input. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with a port mode register 1. if used as input ports, pull-up resistors can be connected to these ports by defining the pull-up resistor option register l. (2) control mode these ports function as a/d converter analog input pins (ani0-ani7). the pull-up resistor is automatically disabled when the pins specified for analog input. 4.2.3 p25 to p27 (port 2) these are 3-bit input/output ports. besides serving as input/output ports, they function as data input/output to/ from the serial interface and clock input/output. the following operating modes can be specified bit-wise. (1) port mode these ports function as 3-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 2. when they are used as input ports, pull-up resistors can be connected to them by defining the pull-up resistor option register l. (2) control mode these ports function as serial interface data input/output and clock input/output. (a) si0, so0, sb0, sb1, sda0, sda1 serial interface serial data input/output pins (b) sck0, scl serial interface serial clock input/output pins caution when this port is used as a serial interface, the i/o and output latches must be set according to the function the user requires. for the setting, refer to figure 16-4 serial operation mode register 0 format.
47 chapter 4 pin function ( m pd78064y subseries) users manual u10105ej4v1um00 4.2.4 p30 to p37 (port 3) these are 8-bit input/output ports. beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 3. when they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register l. (2) control mode these ports function as timer input/output, clock output, and buzzer output. (a) ti1 and ti2 pin for external clock input to the 8-bit timer/event counter. (b) to0 to to2 timer output pins. (c) pcl clock output pin. (d) buz buzzer output pin.
48 chapter 4 pin function ( m pd78064y subseries) users manual u10105ej4v1um00 4.2.5 p70 to p72 (port 7) these are 3-bit input/output ports. beside serving as input/output ports, they function as serial interface data input/ output, clock input/output. the following operating modes can be specified bit-wise. (1) port mode these ports function as 3-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 7. when they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register l. (2) control mode these ports function as serial interface data input/output and clock input/output. (a) si2, so2 serial interface serial data input/output pins (b) sck2 serial interface serial clock input/output pin. (c) rxd, txd asynchronous serial interface serial data input/output pins. (d) asck asynchronous serial interface serial clock input pin. caution when this port is used as a serial interface, the i/o and output latches must be set according to the function the user requires. for the setting, see the operation mode setting list in table 17-2 serial interface channel 2
49 chapter 4 pin function ( m pd78064y subseries) users manual u10105ej4v1um00 4.2.6 p80-p87 (port 8) these are 8-bit input/output ports. beside serving as input/output ports, they function as segment signal output of lcd controller/driver. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input/output ports with port mode register 8. when they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register h. (2) control mode these ports function as segment signal output pins (s32 to s39) of lcd controller/driver. 4.2.7 p90-p97 (port 9) these are 8-bit input/output ports. beside serving as input/output ports, they function as segment signal output of lcd controller/driver. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input/output ports with port mode register 9. when they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register h. (2) control mode these ports function as segment signal output pins (s24 to s31) of lcd controller/driver. 4.2.8 p100-p103 (port 10) these are 4-bit input/output ports. they can be specified bit-wise as input/output ports with port mode register 10. when they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register h. led can be driven directly. 4.2.9 p110-p117 (port 11) these are 8-bit input/output ports. they can be specified bit-wise as input/output ports with port mode register 11. when they are used as input ports, pull-up resistors can be connected by defining the pull-up resistor option register h. test input flag (krif) can be set to 1 by detecting falling edges.
50 chapter 4 pin function ( m pd78064y subseries) users manual u10105ej4v1um00 4.2.10 com0 to com3 these are lcd controller/driver common signal output pins. they output common signals under either of the following conditions: C when the static mode is selected (com0 to com3 outputs) C when 2-time-division (com0, com1 outputs) or 3-time-division (com0 to com2 outputs) operation is performed in 1/2 bias mode C when 3-time-division (com0 to com2 outputs) or 4-time-division (com0 to com3 outputs) operation is performed in 1/3 bias mode 4.2.11 v lc0 -v lc2 these are lcd-driving voltage pins. the mask rom versions can have split resistors by mask option so that lcd driving voltage can be supplied inside the v lc0 -v lc2 pins according to the required bias without connecting external split resistors. 4.2.12 bias these are lcd driving power supply pins. they should be connected to the v lc0 pin to realize user-desired lcd drive voltages to change resistance division ratios, or should be connected to external resistors together with the v lc0 -v lc2 pins and v ss pin to fine-adjust the lcd-driving power voltage. 4.2.13 av ref this pin inputs the reference voltage for the on-chip a/d converter. when not using the a/d converter,connect this pin to the v ss line. 4.2.14 av dd this pin supplies analog voltage for the on-chip a/d converter. even when not using the a/d converter, always use this pin at the same voltage as v dd . 4.2.15 av ss this is a ground voltage pin of a/d converter. always use the same voltage as that of the v ss pin even when a/d converter is not used. 4.2.16 reset this is a low-level active system reset input pin. 4.2.17 x1 and x2 crystal resonator connect pins for main system clock oscillation. for external clock supply, input it to x1 and its inverted signal to x2. 4.2.18 xt1 and xt2 crystal resonator connect pins for subsystem clock oscillation. for external clock supply, input it to xt1 and its inverted signal to xt2.
51 chapter 4 pin function ( m pd78064y subseries) users manual u10105ej4v1um00 4.2.19 v dd positive power supply pin 4.2.20 v ss ground potential pin 4.2.21 v pp ( m pd78p064y only) high-voltage apply pin for prom programming mode setting and program write/verify. connect directly to v ss in normal operating mode. 4.2.22 ic (mask rom version only) the ic (internally connected) pin is provided to set the test mode to check the m pd78064y subseries at delivery. connect it directly to the v ss with the shortest possible wire in the normal operating mode. when a voltage difference is produced between the ic pin and v ss pin because the wiring between those two pins is too long or an external noise is input to the ic pin, the user's program may not run normally. l l connect ic pins to v ss pins directly. v ss ic as short as possible
52 chapter 4 pin function ( m pd78064y subseries) users manual u10105ej4v1um00 input/output circuit type p00/intp0/ti00 2 input connect to v ss . p01/intp1/ti01 p02/intp2 p03/intp3 p04/intp4 p05/intp5 p07/xt1 16 input connect to v dd . p10/ani0 to p17/ani7 11 input/output p25/si0/sb0/sda0 10-a p26/so0/sb1/sda1 p27/sck0/scl p30/to0 5-a p31/to1 p32/to2 p33/ti1 8-a p34/ti2 p35/pcl 5-a p36/buz p37 p70/si2/rxd 8-a p71/so2/txd 5-a p72/sck2/asck 8-a p80/s39-p87/s32 17-a p90/s31-p97/s24 p100-p103 5-a p110-p117 8-a connect independently via a resistor to v dd. s0-s23 17 output open com0-com3 18 v lc0 -v lc2 bias reset 2 input xt2 16 open pin name input/output recommended connection of unused pins 8-a input/output connect independently via a resistor to v ss. 4.3 input/output circuits and recommended connection of unused pins table 4-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. refer to figure 4-1 for the configuration of the input/output circuit of each type. table 4-1. pin input/output circuit types (1/2) * connect independently via a resistor to v dd or v ss .
53 chapter 4 pin function ( m pd78064y subseries) users manual u10105ej4v1um00 pin name input/output recommended connection of unused pins table 4-1. pin input/output circuit types (2/2) input/output circuit type av ref connect to v ss . av dd connect to v dd . av ss connect to v ss . ic (mask rom version) connect directly to v ss . v pp ( m pd78p064y version)
54 chapter 4 pin function ( m pd78064y subseries) users manual u10105ej4v1um00 figure 4-1. pin input/output circuit of list (1/2) type 2 schmitt-triggered input with hysteresis characteristics in type 5-a data output disable p-ch in/out v dd n-ch input enable p-ch v dd pullup enable type 10-a type 11 data output disable p-ch in/out v dd n-ch p-ch v dd pullup enable open drain data output disable p-ch in/out v dd n-ch input enable p-ch v dd pullup enable comparator + p-ch n-ch v ref (threshold voltage) type 8-a data output disable p-ch in/out v dd n-ch p-ch v dd pullup enable feedback cut-off p-ch xt1 xt2 type 16
55 chapter 4 pin function ( m pd78064y subseries) users manual u10105ej4v1um00 type 17 type 18 type 17-a v lc0 v lc1 seg data v lc2 p-ch n-ch p-ch n-ch p-ch n-ch out v lc0 v lc1 com data v lc2 p-ch n-ch p-ch n-ch p-ch n-ch out n-ch p-ch v lc0 v lc1 seg data v lc2 p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch input enable output disable data pullup enable v dd p-ch in/out v dd figure 4-1. pin input/output circuit of list (2/2)
56 users manual u10105ej4v1um00 [memo]
57 users manual u10105ej4v1um00 chapter 5 cpu architecture 5.1 memory spaces figures 5-1 to 5-4 shows memory maps. figure 5-1. memory map ( m pd78062, 78062y) 0000h data memory space general registers 32 x 8 bits internal rom 16384 x 8 bits 3fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area lcd ram 40 x 4 bits reserved program memory space 4000h 3fffh fa58h fa57h fa80h fa7fh fee0h fedfh ff00h feffh ffffh internal high-speed ram 512 x 8 bits special function registers (sfrs) 256 x 8 bits reserved fd00h fcffh
58 chapter 5 cpu architecture users manual u10105ej4v1um00 figure 5-2. memory map ( m pd78063, 78063y) 0000h data memory space general registers 32 x 8 bits i nternal rom 24576 x 8 bits 5fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area lcd ram 40 x 4 bits reserved program memory space 6000h 5fffh fa58h fa57h fa80h fa7fh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 x 8 bits special function registers (sfrs) 256 x 8 bits reserved fb00h faffh
59 chapter 5 cpu architecture users manual u10105ej4v1um00 figure 5-3. memory map ( m pd78064, 78064y) 0000h data memory space general registers 32 x 8 bits internal rom 32768 x 8 bits 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area lcd ram 40 x 4 bits reserved 8000h 7fffh fa58h fa57h fa80h fa7fh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 x 8 bits special function registers (sfrs) 256 x 8 bits reserved fb00h faffh program memory space
60 chapter 5 cpu architecture users manual u10105ej4v1um00 figure 5-4. memory map ( m pd78p064, 78p064y) 0000h data memory space internal prom 32768 x 8 bits 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area lcd ram 40 x 4 bits reserved program memory space 8000h 7fffh fa58h fa57h fa80h fa7fh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 x 8 bits special function registers (sfrs) 256 x 8 bits reserved fb00h faffh general registers 32 x 8 bits
61 chapter 5 cpu architecture users manual u10105ej4v1um00 5.1.1 internal program memory space the internal program memory space stores program data and table data. this space is generally accessed with program counter (pc). the m pd78064, 78064y subseries has on chip rom (or prom) and the capacity of the memory varies depending on the part number. table 5-1. internal rom capacity part number internal rom type capacity m pd78062, 78062y mask rom 16384 x 8 bits m pd78063, 78063y 24576 x 8 bits m pd78064, 78064y 32768 x 8 bits m pd78p064, 78p064y prom the internal program memory is divided into the following three areas. (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vector table area. the reset input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. of the 16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses. table 5-2. vector table vector table address interrupt request 0000h reset input 0004h intwdt 0006h intp0 0008h intp1 000ah intp2 000ch intp3 000eh intp4 0010h intp5 0014h intcsi0 0018h intser 001ah intsr/intcsi2 001ch intst 001eh inttm3 0020h inttm00 0022h inttm01 0024h inttm1 0026h inttm2 0028h intad 003eh brk
62 chapter 5 cpu architecture users manual u10105ej4v1um00 (2) callt instruction table area the 64-byte area 0040h to 007fh can store the subroutine entry address of a 1-byte call instruction (callt). (3) callf instruction entry area the area 0800h to 0fffh can perform a direct subroutine call with a 2-byte call instruction (callf). 5.1.2 internal data memory space the m pd78064 and 78064y subseries units incorporate the following rams. (1) internal high-speed ram the m pd78064, 78064y subseries has on-chip high-speed ram, and the memory capacity varies depending on the part number as shown below. table 5-3. internal high-speed ram capacity part number internal high-speed ram capacity m pd78062, 78062y 512 x 8 bits m pd78063, 78063y 1024 x 8 bits m pd78064, 78064y m pd78p064, 78p064y in this area, four banks of general registers, each bank consisting of eight 8-bit registers, are allocated in the 32-byte area fee0h to feffh. the internal high-speed ram can also be used as a stack. (2) lcd display ram addresses fa58h to fa7fh of 40 x 4 bits are allocated for lcd display ram, however, this area can also be used as general-purpose ram. 5.1.3 special function register (sfr) area an on-chip peripheral hardware special-function register (sfr) is allocated in the area ff00h to ffffh. (refer to table 5-4 ). caution do not access addresses where the sfr is not assigned.
63 chapter 5 cpu architecture users manual u10105ej4v1um00 5.1.4 data memory addressing the m pd78064, 78064y subseries is provided with a variety of addressing modes which take account of memory manipulability, etc. especially at addresses corresponding to data memory area, particular addressing modes are possible to meet the functions of the special function registers (sfrs) and general registers. this area is between fd00h and ffffh for the m pd78062 and 78062y, and between fb00h and ffffh for the other devices. figures 5-5 to 5-8 show the data memory addressing modes. figure 5-5. data memory addressing ( m pd78062, 78062y) 0000h general registers 32 8 bits internal rom 16384 8 bits lcd ram 40 4 bits reserved 4000h 3fffh fa58h fa57h fa80h fa7fh fee0h fedfh ff00h feffh ffffh internal high-speed ram 512 8 bits reserved fd00h fcffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
64 chapter 5 cpu architecture users manual u10105ej4v1um00 figure 5-6. data memory addressing ( m pd78063, 78063y) 0000h general registers 32 8 bits internal rom 24576 8 bits lcd ram 40 4 bits reserved 6000h 5fffh fa58h fa57h fa80h fa7fh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits reserved fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
65 chapter 5 cpu architecture users manual u10105ej4v1um00 figure 5-7. data memory addressing ( m pd78064, 78064y) 0000h general registers 32 8 bits internal rom 32768 8 bits lcd ram 40 4 bits reserved 8000h 7fffh fa58h fa57h fa80h fa7fh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits reserved fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
66 chapter 5 cpu architecture users manual u10105ej4v1um00 figure 5-8. data memory addressing ( m pd78p064, 78p064y) 0000h general registers 32 8 bits internal prom 32768 8 bits lcd ram 40 x 4 bits reserved 8000h 7fffh fa58h fa57h fa80h fa7fh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits reserved fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 x 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
67 chapter 5 cpu architecture users manual u10105ej4v1um00 5.2 processor registers the m pd78064 and 78064y subseries units incorporate the following processor registers. 5.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter, a program status word and a stack pointer. (1) program counter (pc) the program counter is a 16-bit register which holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 5-9. program counter configuration (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically reset upon execution of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 5-10. program status word configuration (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledge operations of the cpu. when 0, the ie is set to di, and only non-maskable interrupt request becomes acknowledgeable. other interrupt requests are all disabled. when 1, the ie is set to ei and interrupt request acknowledge enable is controlled with an inservice priority flag (isp), an interrupt mask flag for various interrupt sources and a priority specification flag. the ie is reset to (0) upon di instruction execution or interrupt acknowledgement and is set to (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set (1). it is reset (0) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information which indicates the register bank selected by sel rbn instruction execution is stored. pc 15 0 70 ie z rbs1 ac rbs0 0 isp cy
68 chapter 5 cpu architecture users manual u10105ej4v1um00 (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable maskable vectored interrupts. when this flag is 0, low-level vectored interrupts specified with a priority specify flag register (pr) are disabled for acknowl- edgement. when it is 1, all interrupts are acknowledgeable. actual acknowledgement is controlled with the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area (fd00h-feffh for the m pd78062 and 78062y, and fb00h-feffh for the other devices) can be set as the stack area. figure 5-11. stack pointer configuration the sp is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. each stack operation saves/resets data as shown in figures 5-12 and 5-13. caution since reset input makes sp contents indeterminate, be sure to initialize the sp before instruction execution. figure 5-12. data to be saved to stack memory 0 15 sp interrupt and brk instruction psw pc15-pc8 pc15-pc8 pc7-pc0 register pair lower sp sp _ 2 sp _ 2 register pair upper call, callf, and callt instruction push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7-pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3
69 chapter 5 cpu architecture users manual u10105ej4v1um00 figure 5-13. data to be reset from stack memory 5.2.2 general registers a general register is mapped at particular addresses (fee0h to feffh) of the data memory. it consists of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l and h). each register can also be used as an 8-bit register. two 8-bit registers can be used in pairs as a 16-bit register (ax, bc, de and hl). they can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set with the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interruption for each bank. reti and retb instruction psw pc15-pc8 pc15-pc8 pc7-pc0 register pair lower sp sp + 2 sp register pair upper ret instruction pop rp instruction sp + 1 pc7-pc0 sp sp + 2 sp sp + 1 sp + 2 sp sp + 1 sp sp + 3
70 chapter 5 cpu architecture users manual u10105ej4v1um00 figure 5-14. general register configuration (a) absolute name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fee0h fee8h bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h (b) function name
71 chapter 5 cpu architecture users manual u10105ej4v1um00 5.2.3 special function register (sfr) unlike a general register, each special-function register has special functions. it is allocated in the ff00h to ffffh area. the special-function register can be manipulated like the general register, with the operation, transfer and bit manipulation instructions. manipulatable bit units, 1, 8 and 16, depend on the special-function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp). when addressing an address, describe an even address. table 5-4 gives a list of special-function registers. the meaning of items in the table is as follows. ? symbol this is a symbol used in assembler (ra78k/0) to indicate an address of the built-in special-function register. it is describable as an instruction operand. ? r/w indicates whether the corresponding special-function register can be read or written. r/w : read/write enable r : read only w : write only ? manipulatable bit units manipulatable bit units, 1, 8, and 16, are indicated. ? after reset indicates each register status upon reset input.
72 chapter 5 cpu architecture users manual u10105ej4v1um00 address special-function register (sfr) name symbol r/w after reset ff00h port0 p0 r/w ?? 00h ff01h port1 p1 ?? ff02h port2 p2 ?? ff03h port3 p3 ?? ff07h port7 p7 ?? ff08h port8 p8 ?? ff09h port9 p9 ?? ff0ah port10 p10 ?? ff0bh port11 p11 ?? ff10h ff11h ff12h ff13h ff14h ff15h ff16h compare register 10 cr10 ? ff17h compare register 20 cr20 ? ff18h 8-bit timer register 1 tm1 ? ff19h 8-bit timer register 2 tm2 ? ff1ah serial i/o shift register 0 sio0 ? ff1fh a/d conversion result register adcr r ? ff20h port mode register 0 pm0 ?? ff21h port mode register 1 pm1 ?? ff22h port mode register 2 pm2 ?? ff23h port mode register 3 pm3 ?? ff27h port mode register 7 pm7 ?? ff28h port mode register 8 pm8 ?? ff29h port mode register 9 pm9 ?? ff2ah port mode register 10 pm10 ?? ff2bh port mode register 11 pm11 ?? ff40h timer clock select register 0 tcl0 ?? 00h ff41h timer clock select register 1 tcl1 ? ff42h timer clock select register 2 tcl2 ? ff43h timer clock select register 3 tcl3 ? 88h ff47h sampling clock select register scs ? 00h ff48h 16-bit timer mode control register tmc0 ?? table 5-4. special-function register list (1/3) manipulatable bit unit 8 bits 1 bit 16 bits capture/compare register 00 cr00 ? undefined capture/compare register 01 cr01 ? 16-bit timer register tm0 r ? 00h r/w undefined tms r 00h ? r/w undefined r/w ffh
73 chapter 5 cpu architecture users manual u10105ej4v1um00 address special-function register (sfr) name symbol r/w after reset ff49h 8-bit timer mode control register tmc1 r/w ?? 00h ff4ah watch timer mode control register tmc2 ?? ff4ch capture/compare control register 0 crc0 ?? 04h ff4eh 16-bit timer output control register toc0 ?? 00h ff4fh 8-bit timer output control register toc1 ?? ff60h serial operating mode register 0 csim0 ?? ff61h serial bus interface control register sbic ?? ff62h slave address register sva ? undefined ff63h interrupt timing specify register sint ?? 00h ff70h asynchronous serial interface mode register asim ?? ff71h asynchronous serial interface status register asis r ?? ff72h serial operating mode register 2 csim2 rw ?? ff73h baud rate generator control register brgc ? ff74h transmit shift register txs sio2 w ? ffh receive buffer register rxb r ff80h a/d converter mode register adm r/w ?? 01h ff84h a/d converter input select register adis ? 00h ffb0h lcd display mode register lcdm ?? ffb2h lcd display control register lcdc ?? ffb8h key return mode register krm ?? 02h ffe0h interrupt request flag register 0l if0 if0l ?? ? 00h ffe1h interrupt request flag register 0h if0h ?? ffe2h interrupt request flag register 1l if1l ?? ffe4h interrupt mask flag register 0l mk0 mk0l ?? ? ffh ffe5h interrupt mask flag register 0h mk0h ?? ffe6h interrupt mask flag register 1l mk1l ?? ffe8h priority order specify flag register 0l pr0 pr0l ?? ? ffe9h priority order specify flag register 0h pr0h ?? ffeah priority order specify flag register 1l pr1l ?? ffech external interrupt mode register 0 intm0 ? 00h ffedh external interrupt mode register 1 intm1 ? fff0h memory size switching register ims ? (note) fff2h oscillation mode selection register osms w ? 00h fff3h pull-up resistor option register h puoh r/w ?? table 5-4. special-function register list (2/3) manipulatable bit unit 8 bits 1 bit 16 bits
74 chapter 5 cpu architecture users manual u10105ej4v1um00 address special-function register (sfr) name symbol r/w after reset fff7h pull-up resistor option register l puol ?? 00h fff9h watchdog timer mode register wdtm ?? fffah oscillation stabilization time select register osts ? 04h fffbh processor clock control register pcc ?? table 5-4. special-function register list (3/3) manipulatable bit unit 8 bits 1 bit 16 bits r/w note the value after reset depends on products. m pd78062, 78062y: 44h, m pd78063, 78063y: c6h, m pd78064, 78064y: c8h, m pd78p064, 78p064y: c8h.
75 chapter 5 cpu architecture users manual u10105ej4v1um00 5.3 instruction address addressing an instruction address is determined by program counter (pc) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing. (for details of instructions, refer to 78k/0 user's manual: instruction (ieu-1372) . 5.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed two's complement data (C128 to +127) and bit 7 becomes a sign bit. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc a jdisp8 when s = 0, all bits of a are 0. when s = 1, all bits of a are 1. pc indicates the start address of the instruction after the br instruction. ...
76 chapter 5 cpu architecture users manual u10105ej4v1um00 5.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. [illustration] in the case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr. in the case of callf !addr11 instruction 15 0 pc 87 70 fa 10? 11 10 00001 643 callf fa 7?
77 chapter 5 cpu architecture users manual u10105ej4v1um00 5.3.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. this function is carried out when the callt [addr5] instruction is executed. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4? operation code
78 chapter 5 cpu architecture users manual u10105ej4v1um00 5.3.4 register addressing [function] register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
79 chapter 5 cpu architecture users manual u10105ej4v1um00 5.4 operand address addressing the following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 implied addressing [function] the register which functions as an accumulator (a and ax) in the general register is automatically addressed. of the m pd78064 and 78064y subseries instruction words, the following instructions employ implied addressing. instruction register to be specified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric values which become decimal correction targets ror4/rol4 a register for storage of digit data which undergoes digit rotation [operand format] because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the product of a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing.
80 chapter 5 cpu architecture users manual u10105ej4v1um00 5.4.2 register addressing [function] the general register to be specified is accessed as an operand with the register specify code (rn and rpn) of an instruction word in the registered bank specified with the register bank select flag (rbs0 to rbs1). register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl 'r' and 'rp' can be described with function names (x, a, c, b, e, d, l, h, ax, bc, de and hl) as well as absolute names (r0 to r7 and rp0 to rp3). [description example] mov a, c; when selecting c register as r operation code 01100010 incw de; when selecting de register pair as rp operation code 10000100
81 chapter 5 cpu architecture users manual u10105ej4v1um00 5.4.3 direct addressing [function] the memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !fe00h; when setting !addr16 to fe00h operation code 10001110 00000000 11111110
82 chapter 5 cpu architecture users manual u10105ej4v1um00 5.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. this addressing is applied to the 256-byte space fe20h to ff1fh. an internal ram and a special-function register (sfr) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. if the sfr area (ff00h to ff1fh) where short direct addressing is applied, ports which are frequently accessed in a program and a compare register of the timer/event counter and a capture register of the timer/event counter are mapped and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. [operand format] identifier description saddr label of fe20h to ff1fh immediate data saddrp label of fe20h to ff1fh immediate data (even address only)
83 chapter 5 cpu architecture users manual u10105ej4v1um00 [description example] mov fe30h, #50h; when setting saddr to fe30h and immediate data to 50h operation code 00010001 00110000 01010000 [illustration] when 8-bit immediate data is 20h to ffh, a = 0 when 8-bit immediate data is 00h to 1fh, a = 1 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset a
84 chapter 5 cpu architecture users manual u10105ej4v1um00 5.4.5 special-function register (sfr) addressing [function] the memory-mapped special-function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfr mapped at ff00h to ff1fh can be accessed with short direct addressing. [operand format] identifier description sfr special-function register name sfrp 16-bit manipulatable special-function register name (even address only) [description example] mov pm0, a; when selecting pm0 as sfr operation code 11110110 00100000 [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
85 chapter 5 cpu architecture users manual u10105ej4v1um00 5.4.6 register indirect addressing [function] register pair contents specified with a register pair specify code in an instruction word of the register bank specified with a register bank select flag (rbs0 and rbs1) serve as an operand address for addressing the memory to be manipulated. this addressing can be carried out for all the memory spaces. [operand format] identifier description [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair operation code 10000101 [illustration] 16 0 8 d 7 e 0 7 7 0 a de
86 chapter 5 cpu architecture users manual u10105ej4v1um00 5.4.7 based addressing [function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the hl register pair in an instruction word of the register bank specified with the register bank select flag (rbs0 and rbs1) and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl + byte] [description example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000
87 chapter 5 cpu architecture users manual u10105ej4v1um00 5.4.8 based indexed addressing [function] the b or c register contents specified in an instruction are added to the contents of the base register, that is, the hl register pair in an instruction word of the register bank specified with the register bank select flag (rbs0 and rbs1) and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl + b], [hl + c] [description example] in the case of mov a, [hl + b] operation code 10101011 5.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. stack addressing enables to address the internal high-speed ram area only. [description example] in the case of push de operation code 10110101
88 users manual u10105ej4v1um00 memo
89 users manual u10105ej4v1um00 chapter 6 port functions 6.1 port functions the m pd78064 and 78064y subseries units incorporate two input ports and 55 input/output ports. figure 6-1 shows the port configuration. every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. besides port functions, the ports can also serve as on-chip hardware input/output pins. figure 6-1. port types port 9 port 0 port 10 port 1 port 2 p00 p90 p97 p100 p103 p10 p07 p17 p25 p27 port 3 p110 p117 port 11 p30 p37 port 8 p80 p87 p05 port 7 p70 p72
90 chapter 6 port functions users manual u10105ej4v1um00 table 6-1. port functions ( m pd78064 subseries) pin name function dual-function pin p00 port 0. input only intp0/ti00 p01 7-bit input/output port. input/output mode can be specified bitwise. intp1/ti01 p02 if used as an input port, a pull-up resistor intp2 p03 can be connected by software. intp3 p04 intp4 p05 intp5 p07 input only xt1 p10 to p17 port 1. ani0 to ani7 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. p25 port 2. si0/sb0 p26 3-bit input/output port. input/output mode can be specified bit-wise. so0/sb1 p27 if used as an input port, a pull-up resistor can be connected by software. sck0 p30 port 3. to0 p31 8-bit input/output port. input/output mode can be specified bit-wise. to1 p32 if used as an input port, a pull-up resistor can be connected by software. to2 p33 ti1 p34 ti2 p35 pcl p36 buz p37 p70 port 7. si2/rxd p71 3-bit input/output port. input/output mode can be specified bit-wise. so2/txd p72 if used as an input port, a pull-up resistor can be connected by software. sck2/asck p80 to p87 port 8. s39-s32 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. this port can be used as a segment signal output port or an i/o port in 2-bit units by setting lcd control register. p90 to p97 port 9. s31-s24 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. this port can be used as a segment signal output port or an i/o port in 2-bit units by setting lcd control register. p100 to p103 port 10. 4-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. this port can directly drive leds. p110 to p117 port 11. 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. falling edge detection is possible.
91 chapter 6 port functions users manual u10105ej4v1um00 table 6-2. port functions ( m pd78064y subseries) pin name function dual-function pin p00 port 0. input only intp0/ti00 p01 7-bit input/output port. input/output mode can be specified bitwise. intp1/ti01 p02 if used as an input port, a pull-up resistor intp2 p03 can be connected by software. intp3 p04 intp4 p05 intp5 p07 input only xt1 p10 to p17 port 1. ani0 to ani7 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. p25 port 2. si0/sb0 p26 3-bit input/output port. input/output mode can be specified bit-wise. so0/sb1 p27 if used as an input port, a pull-up resistor can be connected by software. sck0 p30 port 3. to0 p31 8-bit input/output port. input/output mode can be specified bit-wise. to1 p32 if used as an input port, a pull-up resistor can be connected by software. to2 p33 ti1 p34 ti2 p35 pcl p36 buz p37 p70 port 7. si2/rxd p71 3-bit input/output port. input/output mode can be specified bit-wise. so2/txd p72 if used as an input port, a pull-up resistor can be connected by software. sck2/asck p80 to p87 port 8. s39-s32 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. this port can be used as a segment signal output port or an i/o port in 2-bit units by setting lcd control register. p90 to p97 port 9. s31-s24 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. this port can be used as a segment signal output port or an i/o port in 2-bit units by setting lcd control register. p100 to p103 port 10. 4-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. this port can directly drive leds. p110 to p117 port 11. 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, a pull-up resistor can be connected by software. falling edge detection is possible.
92 chapter 6 port functions users manual u10105ej4v1um00 6.2 port configuration a port consists of the following hardware: table 6-3. port configuration item configuration control register port mode register (pmm: m = 0 to 3, 7 to 11) pull-up resistor option register (puoh, puol) key return mode register (krm) port total: 57 ports (2 inputs, 55 inputs/outputs) pull-up resistor total: 55 (software specifiable: 55) 6.2.1 port 0 port 0 is an 7-bit input/output port with output latch. p01 to p05 pins can specify the input mode/output mode in 1-bit units with the port mode register 0. p00 and p07 pins are input-only ports. when p01 to p05 pins are used as input ports, a pull-up resistor can be connected to them in 5-bit units with a pull-up resistor option register l. dual-functions include external interrupt input, external count clock input to the timer and crystal connection for subsystem clock oscillation. reset input sets port 0 to input mode. figures 6-2 and 6-3 show block diagrams of port0. caution because port 0 also serves for external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. thus, when the output mode is used, set the interrupt mask flag to 1.
93 chapter 6 port functions users manual u10105ej4v1um00 figure 6-2. p00 and p07 configurations figure 6-3. p01 to p05 configurations puo : pull-up resistor option register pm : port mode register rd : port 0 read signal wr : port 0 write signal p00/intp0/ti00, p07/xt1 rd internal bus p-ch wr pm wr port rd wr puo v dd p01/intp1/ti01. p02/intp2 p05/intp5 selector puo0 output latch (p01 to p05) pm01-pm05 internal bus
94 chapter 6 port functions users manual u10105ej4v1um00 6.2.2 port 1 port 1 is an 8-bit input/output port with output latch. it can specify the input mode/output mode in 1-bit units with a port mode register 1. when p10 to p17 pins are used as input ports, a pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register l. dual-functions include an a/d converter analog input. reset input sets port 1 to input mode. figure 6-4 shows a block diagram of port 1. caution a pull-up resistor cannot be used for pins used as a/d converter analog input. figure 6-4. p10 to p17 configurations puo : pull-up resistor option register pm : port mode register rd : port 1 read signal wr : port 1 write signal p-ch wr pm wr port rd wr puo v dd p10/ani0, p17/ani7 selector puo1 output latch (p10 to p17) pm10-pm17 internal bus
95 chapter 6 port functions users manual u10105ej4v1um00 6.2.3 port 2 ( m pd78064 subseries) port 2 is an 3-bit input/output port with output latch. p25 to p27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2. when p25 to p27 pins are used as input ports, a pull-up resistor can be connected to them in 3-bit units with a pull-up resistor option register l. dual-functions include serial interface data input/output and clock input/output. reset input sets port 2 to input mode. figures 6-5 and 6-6 show a block diagram of port 2. cautions 1. when used as a serial interface, set the input/output and output latch according to its functions. for the setting method, refer to figure 15-4 serial operating mode register 0 format. 2. when reading the pin state in sbi mode, set pm2n to 1 (n = 5, 6) (refer to the description of (10) sbi mode precautions (e) in section 15.4.3 sbi mode operation). figure 6-5. p25, p26 configurations ( m pd78064 subseries) puo : pull-up resistor option register pm : port mode register rd : port 2 read signal wr : port 2 write signal p-ch wr pm wr port rd wr puo v dd selector puo2 output latch (p25, p26) pm25, pm26 internal bus alternate function p25/si0/sb0, p26/so0/sb1
96 chapter 6 port functions users manual u10105ej4v1um00 figure 6-6. p27 configuration ( m pd78064 subseries) puo : pull-up resistor option register pm : port mode register rd : port 2 read signal wr : port 2 write signal p-ch wr pm wr port rd wr puo v dd selector puo2 output latch (p27) pm27 internal bus alternate function p27/sck0
97 chapter 6 port functions users manual u10105ej4v1um00 6.2.4 port 2 ( m pd78064y subseries) port 2 is an 3-bit input/output port with output latch. p25 to p27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2. when p25 to p27 pins are used as input ports, a pull-up resistor can be connected to them in 3-bit units with a pull-up resistor option register l. dual-functions include serial interface data input/output and clock input/output. reset input sets port 2 to input mode. figures 6-7 and 6-8 show a block diagram of port 2. caution when used as a serial interface, set the input/output and output latch according to its functions. for the setting method, refer to figure 16-4 serial operating mode register 0 format. figure 6-7. p25, p26 configurations ( m pd78064y subseries) puo : pull-up resistor option register pm : port mode register rd : port 2 read signal wr : port 2 write signal p-ch wr pm wr port rd wr puo v dd selector puo2 output latch (p25, p26) pm25, pm26 internal bus alternate function p25/si0/sb0/sda0, p26/so0/sb1/sda1
98 chapter 6 port functions users manual u10105ej4v1um00 figure 6-8. p27 configuration ( m pd78064y subseries) puo : pull-up resistor option register pm : port mode register rd : port 2 read signal wr : port 2 write signal p-ch wr pm wr port rd wr puo v dd selector puo2 output latch (p27) pm27 internal bus alternate function p27/sck0/scl
99 chapter 6 port functions users manual u10105ej4v1um00 6.2.5 port 3 port 3 is an 8-bit input/output port with output latch. p30 to p37 pins can specify the input mode/output mode in 1-bit units with the port mode register 3. when p30 to p37 pins are used as input ports, a pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register l. dual-functions include timer input/output, clock output and buzzer output. reset input sets port 3 to input mode. figure 6-9 shows a block diagram of port 3. figure 6-9. p30 to p37 configurations puo : pull-up resistor option register pm : port mode register rd : port 3 read signal wr : port 3 write signal p-ch wr pm wr port rd wr puo v dd selector puo3 output latch (p30 to p37) pm30-pm37 internal bus alternate function p30/to0 p32/to2, p33/ti1, p34/ti2, p35/pcl, p36/buz, p37
100 chapter 6 port functions users manual u10105ej4v1um00 6.2.6 port 7 this is a 3-bit input/output port with output latches. input mode/output mode can be specified bit-wise by means of port mode register 7. when pins p70 to p72 are used as input port pins, a pull-up resistor can be connected as a 3-bit unit by means of pull-up resistor option register l. dual-functions include serial interface channel 2 data input/output and clock input/output. reset input sets the input mode. port 7 block diagrams are shown in figures 6-10 and 6-11. caution when used as a serial interface, set the input/output and output latch according to its functions. for the setting method, refer to table 17-2 serial interface channel 2 operating mode setting. figure 6-10. p70 configuration puo : pull-up resistor option register pm : port mode register rd : port 7 read signal wr : port 7 write signal p-ch wr pm wr port rd wr puo v dd selector puo7 output latch (p70) pm70 internal bus p70/si2/rxd
101 chapter 6 port functions users manual u10105ej4v1um00 figure 6-11. p71 and p72 configurations puo : pull-up resistor option register pm : port mode register rd : port 7 read signal wr : port 7 write signal p-ch wr pm wr port rd wr puo v dd selector puo7 output latch (p71 and p72) pm71, pm72 internal bus alternate function p71/so2/txd, p72/sck2/asck
102 chapter 6 port functions users manual u10105ej4v1um00 6.2.7 port 8 this is an 8-bit input/output port with output latches. input mode/output mode can be specified bit-wise by means of port mode register 8. when pins p80 to p87 are used as input port pins, a pull-up resistor can be connected as an 8-bit unit by means of pull-up resistor option register h. these pins are dual-function pins and serve as lcd controller/driver segment signal outputs. reset input sets the input mode. the port 8 block diagram is shown in figure 6-12. figure 6-12. p80 to p87 configurations puo : pull-up resistor option register pm : port mode register rd : port 8 read signal wr : port 8 write signal p-ch wr pm wr port rd wr puo v dd selector puo8 output latch (p80 to p87) pm80 to pm87 internal bus p80/s39 p87/s32
103 chapter 6 port functions users manual u10105ej4v1um00 6.2.8 port 9 this is a 8-bit input/output port with output latches. input mode/output mode can be specified bit-wise by means of port mode register 9. when pins p90 and p97 are used as input port pins, a pull-up resistor can be connected as a 8-bit unit by means of pull-up resistor option register h. these pins are dual-function pins and serve as lcd controller/driver segment signal outputs. reset input sets the input mode. the port 9 block diagram is shown in figure 6-13. figure 6-13. p90 to p97 configurations puo : pull-up resistor option register pm : port mode register rd : port 9 read signal wr : port 9 write signal p-ch wr pm wr port rd wr puo v dd selector puo9 output latch (p90 and p97) pm90, pm97 internal bus p90/s31 p97/s24
104 chapter 6 port functions users manual u10105ej4v1um00 6.2.9 port 10 this is a 4-bit input/output port with output latches. input mode/output mode can be specified bit-wise by means of port mode register 10. when pins p100 and p103 are used as input port pins, a pull-up resistor can be connected as a 4-bit unit by means of pull-up resistor option register h. reset input sets the input mode. the port 10 block diagram is shown in figure 6-14. figure 6-14. p100 to p103 configurations puo : pull-up resistor option register pm : port mode register rd : port 9 read signal wr : port 9 write signal p-ch wr pm wr port rd wr puo v dd selector puo10 output latch (p100 to p103) pm100 to pm103 internal bus p100-p103
105 chapter 6 port functions users manual u10105ej4v1um00 6.2.10 port 11 port 11 is an 8-bit input/output port with output latches. p110 to p117 pins can specify the input mode/output mode in 8-bit units with the port mode register 11. when they are used as input ports, a pull-up resistor can be connected to them in 8-bit units with pull-up resistor option register h. the test input flag (krif) can be set to 1 by detecting falling edges. dual-functions include address/data bus function in external memory expansion mode. reset input sets port 11 to input mode. figures 6-15 and 6-16 show the block diagrams of port 4 and falling edge detection circuit, respectively. figure 6-15. p40 to p47 configurations puo : pull-up resistor option register mm : memory expansion mode register rd : port 4 read signal wr : port 4 write signal figure 6-16. block diagram of falling edge detection circuit standby release signal krif setting signal p110 p111 p112 p113 p114 p115 p116 p117 falling edge detection circuit krmk p-ch wr pm wr port rd wr puo v dd selector puo11 output latch (p110 to p117) pm110 to pm117 internal bus p110-p117
106 chapter 6 port functions users manual u10105ej4v1um00 6.3 port function control registers the following three types of registers control the ports. ? port mode registers (pm0 to pm3, pm7 to pm11) ? pull-up resistor option register (puoh, puol) ? key return mode register (krm) (1) port mode registers (pm0 to pm3, pm7 to pm11) these registers are used to set port input/output in 1-bit units. pm0 to pm3 and pm7 to pm11 are independently set with a 1-bit or 8-bit memory manipulation instruction reset input sets registers to ffh. when port pins are used as the dual-function pins, set the port mode register and output latch according to table 6-4. cautions 1. pins p00 and p07 are input-only pins. 2. as port 0 has a dual function as external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. when the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand.
107 chapter 6 port functions users manual u10105ej4v1um00 table 6-4. port mode register and output latch settings when using dual-functions p00 intp0 input 1 (fixed) none ti00 input 1 (fixed) none p01 intp1 input 1 ti01 input 1 p02 to p05 intp2 to intp5 input 1 p07 note1 xt1 input 1 (fixed) none p10 to p17 note1 ani0 to ani7 input 1 p30 to p32 to0 to to2 output 0 0 p33, p34 ti1, ti2 input 1 p35 pcl output 0 0 p36 buz output 0 0 p80 to p87 s39 to s32 output note2 p90 to p97 s31 to s24 output note2 dual-functions name p pm input/output pin name notes 1. if these ports are read out when these pins are used in the alternative function mode, undefined values are read. 2. when the p80 to p87 and p90 to p97 pins are used for dual functions, set the function by the lcd display control register. caution when port 2 and port 7 are used for serial interface, the i/o latch or output latch must be set according to its function. for the setting methods, see figure 15-4 serial operation mode register 0 format, figure 16-4 serial operation mode register 0 format, and table 17-2 serial interface channel 2 operating mode settings. remarks : dont care pm : port mode register p : port output latch
108 chapter 6 port functions users manual u10105ej4v1um00 figure 6-17. port mode register format pm0 pm1 pm2 1 1 pm03 pm02 pm01 1 76543210 symbol pm3 pm8 ff20h ff21h ff22h ff23h ff28h ffh ffh ffh ffh ffh r/w r/w r/w r/w r/w address after reset r/w pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm27 pm26 pm25 1 1 1 1 1 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm87 pm86 pm85 pm84 pm83 pm82 pm81 pm80 pm9 pm7 ff29h ff27h ffh ffh r/w r/w pm97 pm96 pm95 pm94 pm93 pm92 pm91 pm90 1 1 1 1 1 pm72 pm71 pm70 pm05 pm04 pm11 pm10 pmmn pmn pin input/output mode selection (m = 0-3, 7-11 : n = 0-7) 0 1 output mode (output buffer on) input mode (output buffer off) ff2ah ff2bh ffh ffh r/w r/w pm112 pm111 pm110 1111 pm101 pm100 pm115 pm114 pm113 pm117 pm116 pm103 pm102 *
109 chapter 6 port functions users manual u10105ej4v1um00 (2) pull-up resistor option register (puoh, puol) this register is used to set whether to use an internal pull-up resistor at each port or not. a pull-up resistor is internally used at bits which are set to the input mode at a port where pull-up resistor use has been specified with puoh, puol. no pull-up resistors can be used to the bits set to the output mode or to the bits used as an analog input pin, irrespective of puoh or puol setting. puoh and puol are set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. cautions 1. p00 and p07 pins do not incorporate a pull-up resistor. 2. when ports 1, 8, and 9 are used as dual-function pins, a pull-up resistor cannot be used even if 1 is set in puom (m = 1, 8, 9). figure 6-18. pull-up resistor option register format caution zeros must be set to bits 4 to 7 of puoh and bit 4 to 6 of puol. puo7 puo2 puo1 puo0 puol puom pm internal pull-up resistor selection (m = 0-3, 7-11) 0 1 internal pull-up resistor not used internal pull-up resistor used fff7h 00h r/w 76 54 puo3 76 3 2 0 1 00 puo11 puo10 0 puoh fff3h 00h r/w 76 54 symbol address after reset r/w 0 76 3 2 0 1 puo9 puo8 0 0 0
110 chapter 6 port functions users manual u10105ej4v1um00 (3) key return mode register (krm) this register sets enabling/disabling of standby function release by a key return signal (falling edge detection of port 11), and selects the port 11 falling edge input. krm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets krm to 02h. figure 6-19. key return mode register format caution when falling edge detection of port 11 is used, krif should be cleared to 0 (not cleared to 0 automatically). krif key return signal detection flag 0 1 not detected detected (falling edge detection of port 11) 000 krm ffb8h 76 5432 symbol 1 0 krmk krif 0 address after reset r/w 02h r/w krmk standby mode control by key return signal 0 1 standby mode release enabled standby mode release disabled krm3 selection of port 11 falling edge input 0 0 p117 krm2 0 1 1 1 0 1 p114-p117 p112-p117 p110-p117 krm3 krm2
111 chapter 6 port functions users manual u10105ej4v1um00 6.4 port function operations port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 writing to input/output port (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is retained until data is written to the output latch again. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined except for the manipulated bit. 6.4.2 reading from input/output port (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode the pin status is read by a transfer instruction. the output latch contents do not change. 6.4.3 operations on input/output port (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode the output latch contents are undefined, but since the output buffer is off, the pin status does not change. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit.
112 users manual u10105ej4v1um00 [memo]
113 users manual u10105ej4v1um00 chapter 7 clock generator 7.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators are available. (1) main system clock oscillator this circuit oscillates at frequencies of 1 to 5.0 mhz. oscillation can be stopped by executing the stop instruction or setting the processor clock control register. (2) subsystem clock oscillator the circuit oscillates at a frequency of 32.768 khz. oscillation cannot be stopped. if the subsystem clock oscillator is not used, not using the internal feedback resistance can be set by the processor clock control register. this enables to decrease power consumption in the stop mode. 7.2 clock generator configuration the clock generator consists of the following hardware. table 7-1. clock generator configuration item configuration processor clock control register (pcc) oscillation mode selection register (osms) main system clock oscillator subsystem clock oscillator control register oscillator
114 chapter 7 clock generator users manual u10105ej4v1um00 figure 7-1. block diagram of clock generator subsystem clock oscillator main system clock oscillator x2 x1 xt2 xt1/p07 frc stop mcc frc cls css pcc2 pcc1 internal bus standby control circuit to intp0 sampling clock 2 f xx 2 2 f xx 2 3 f xx 2 4 f xx prescaler clock to peripheral hardware prescaler oscillation mode selection register watch timer, clock output function f xx cpu clock (f cpu ) scaler selector f x f xt 2 f x mcs processor clock control register 2 f xt pcc0 3 selector 1/2
115 chapter 7 clock generator users manual u10105ej4v1um00 7.3 clock generator control register the clock generator is controlled by the following two registers: ? processor clock control register (pcc) ? oscillation mode selection register (osms) (1) processor clock control register (pcc) the pcc sets whether to use cpu clock selection, the ratio of division, main system clock oscillator operation/ stop and subsystem clock oscillator internal feedback resistor. the pcc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets the pcc to 04h. figure 7-2. subsystem clock feedback resistor frc p-ch feedback resistor xt1 xt2
116 chapter 7 clock generator users manual u10105ej4v1um00 figure 7-3. processor clock control register format mcc frc cls css pcc2 pcc1 pcc0 pcc cls 0 1 main system clock subsystem clock fffbh 04h r/w note 1 76 54 symbol address after reset r/w 0 76 3 2 0 1 css 0 0f xx /2 pcc2 cpu ciock selection (f cpu ) pcc1 pcc0 cpu clock status 0 0 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 f xx /2 2 f xx /2 3 f xx /2 4 f xt /2 (122 s) f xx setting prohibited other than above frc 0 1 internal feedback resistor used internal feedback resistor not used subsystem clock feedback resistor selection mcc 0 1 oscillation possible oscillation stopped main system clock oscillation control note 2 r/w r/w r/w r f x /2 (0.8 s) m f x /2 2 (1.6 s) m f x /2 3 (3.2 s) m f x /2 4 (6.4 s) m f x (0.4 s) m f x /2 2 (1.6 s) m f x /2 3 (3.2 s) m f x /2 4 (6.4 s) m f x /2 5 (12.8 s) m f x /2 (0.8 s) m m mcs=1 mcs=0 0 1 notes 1. bit 5 is read only. 2. when the cpu is operating on the subsystem clock, mcc should be used to stop the main system clock oscillation. a stop instruction should not be used. caution bit 3 must be set to 0. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. mcs : bit 0 of oscillation mode selection register 5. figures in parentheses indicate minimum instruction execution time : 2f cpu when operating at f x = 5.0 mhz or f xt = 32.768 khz.
117 chapter 7 clock generator users manual u10105ej4v1um00 (2) oscillation mode selection register (osms) this register specifies whether the clock output from the main system clock oscillator without passing through the scaler is used as the main system clock, or the clock output via the scaler is used as the main system clock. osms is set with 8-bit memory manipulation instruction. reset input sets osms to 00h. figure 7-4. oscillation mode selection register format mcs main system clock scaler control 0 1 scaler used scaler not used 000 0 osms fff2h 76 5432 symbol 1 0 mcs 0 0 address after reset r/w 00h w 0 cautions 1. writing to osms should be performed only immediately after reset signal release and before peripheral hardware operation starts. as shown in figure 7-5 below, writing data (including same data as previous) to osms cause delay of main system clock cycle up to 2/f x during the write operation. therefore, if this register is written during the operation, in peripheral hardware which operates with the main system clock, a temporary error occurs in the count clock cycle of timer, etc. in addition, because the oscillation mode is changed by this register, the clocks for peripheral hardware as well as that for the cpu are switched. 2. when writing 1 to mcs, v dd must be 2.7 v or higher before the write execution. figure 7-5. main system clock waveform due to writing to osms remark f xx : main system clock frequency (fx or fx/2) f x : main system clock oscillation frequency write to osms (mcs 0) f xx max. 2/f x operating at f xx = f x /2 (mcs = 0) operating at f xx = f x /2 (mcs = 0) *
118 chapter 7 clock generator users manual u10105ej4v1um00 7.4 system clock oscillator 7.4.1 main system clock oscillator the main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 mhz) connected to the x1 and x2 pins. external clocks can be input to the main system clock oscillator. in this case, input a clock signal to the x1 pin and an antiphase clock signal to the x2 pin. figure 7-6 shows an external circuit of the main system clock oscillator. figure 7-6. external circuit of main system clock oscillator (a) crystal and ceramic oscillation (b) external clock caution do not execute the stop instruction or do not set mcc to 1 if an external clock is used. this is because the x2 pin is connected to v dd via a pull-up resistor. crystal or ceramic resonator ic x1 x2 x1 pd74hcu04 m x2 external clock *
119 chapter 7 clock generator users manual u10105ej4v1um00 7.4.2 subsystem clock oscillator the subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 khz) connected to the xt1 and xt2 pins. external clocks can be input to the subsystem clock oscillator. in this case, input a clock signal to the xt1 pin and an antiphase clock signal to the xt2 pin. figure 7-7 shows an external circuit of the subsystem clock oscillator. figure 7-7. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock cautions 1. when using a main system clock oscillator and a subsystem clock oscillator, carry out wiring in the broken line area in figures 7-6 and 7-7 to prevent any effects from wiring capacities. l minimize the wiring length. l do not allow wiring to intersect with other signal conductors. do not allow wiring to come near changing high current. l set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground to any ground pattern where high current is present. l do not fetch signals from the oscillator. take special note of the fact that the subsystem clock oscillator is a circuit with low-level amplification so that current consumption is maintained at low levels. figure 7-8 shows examples of oscillator having bad connection. figure 7-8. examples of oscillator with bad connection (1/2) (a) wiring of connection (b) signal conductors intersect circuits is too long each other remark when using a subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. further, insert resistors in series on the side of xt2. x2 x1 portn (n=0-3, 7-11) ic ic x2 x1 external clock xt1 xt2 pd74hcu04 m xt1 xt2 32.768 khz ic
120 chapter 7 clock generator users manual u10105ej4v1um00 figure 7-8. examples of oscillator with bad connection (2/2) (c) changing high current is too near a (d) current flows through the grounding line signal conductor of the oscillator (potential at points a, b, and c fluctuate) (e) signals are fetched (f) signal conductors of the main and sub system clocks are parallel and near each other remark when using a subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. cautions 2. in figure 7-8 (f), xt1 and x1 are wired in parallel. thus, the cross-talk noise of x1 may increase with xt1, resulting in malfunctioning. to prevent that from occurring, it is recommended to wire xt1 and x1 so that they are not in parallel. ic x2 x1 high current ic x2 ab c pnm v dd high current x1 ic x2 x1 ic x2 x1 xt1 xt2 xt1 and x1 are wiring in parallel
121 chapter 7 clock generator users manual u10105ej4v1um00 7.4.3 scaler the scaler divides the main system clock oscillator output (f xx ) and generates various clocks. 7.4.4 when no subsystem clocks are used if it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the xt1 and xt2 pins as follows. xt1 : connect to v dd xt2 : open in this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops. to minimize leakage current, the above internal feedback resistance can be removed with bit 6 (frc) of the processor clock control register. in this case also, connect the xt1 and xt2 pins as described above. *
122 chapter 7 clock generator users manual u10105ej4v1um00 7.5 clock generator operations the clock generator generates the following various types of clocks and controls the cpu operating mode including the standby mode. ? main system clock f xx ? subsystem clock f xt ? cpu clock f cpu ? clock to peripheral hardware the following clock generator functions and operations are determined with the processor clock control register (pcc) and the oscillation mode selection register (osms). (a) upon generation of reset signal, the lowest speed mode of the main system clock (12.8 m s when operated at 5.0 mhz) is selected (pcc = 04h, osms = 00h). main system clock oscillation stops while low level is applied to reset pin. (b) with the main system clock selected, one of the six cpu clock types (0.4 m s. 0.8 m s, 1.6 m s, 3.2 m s, 6.4 m s, 12.8 m s @ 5.0 mhz) can be selected by setting the pcc and osms. (c) with the main system clock selected, two standby modes, the stop and halt modes, are available. to decrease current consumption in the stop mode, the subsystem clock feedback resistor can be disconnected to stop the subsystem clock. (d) the pcc can be used to select the subsystem clock and to operate the system with low current consumption (122 m s when operated at 32.768 khz). (e) with the subsystem clock selected, main system clock oscillation can be stopped with the pcc. the halt mode can be used. however, the stop mode cannot be used. (subsystem clock oscillation cannot be stopped.) (f) the main system clock is divided and supplied to the peripheral hardware. the subsystem clock is supplied to 16-bit timer/event counter, the watch timer, and clock output functions only. thus, 16-bit timer/event counter (when selecting watch timer output for count clock operating with subsystem clock), the watch function, and the clock output function can also be continued in the standby state. however, since all other peripheral hardware operate with the main system clock, the peripheral hardware also stops if the main system clock is stopped. (except external input clock operation)
123 chapter 7 clock generator users manual u10105ej4v1um00 7.5.1 main system clock operations when operated with the main system clock (with bit 5 (cls) of the processor clock control register (pcc) set to 0), the following operations are carried out by pcc setting. (a) because the operation guarantee instruction execution speed depends on the power supply voltage, the instruction execution time can be changed by bit 0 to bit 2 (pcc0 to pcc2) of the pcc. (b) if bit 7 (mcc) of the pcc is set to 1 when operated with the main system clock, the main system clock oscillation does not stop. when bit 4 (css) of the pcc is set to 1 and the operation is switched to subsystem clock operation (cls = 1) after that, the main system clock oscillation stops (see figure 7-9 ). figure 7-9. main system clock stop function (1/2) (a) operation when mcc is set after setting css with main system clock operation (b) operation when mcc is set in case of main system clock operation mcc css cls main system clock oscillation subsystem clock oscillation cpu clock l l oscillation does not stop. mcc css cls main system clock oscillation subsystem clock oscillation cpu clock
124 chapter 7 clock generator users manual u10105ej4v1um00 figure 7-9. main system clock stop function (2/2) (c) operation when css is set after setting mcc with main system clock operation mcc css cls main system clock oscillation subsystem clock oscillation cpu clock 7.5.2 subsystem clock operations when operated with the subsystem clock (with bit 5 (cls) of the processor clock control register (pcc) set to 1), the following operations are carried out. (a) the instruction execution time remains constant (122 m s when operated at 32.768 khz) irrespective of bit 0 to bit 2 (pcc0 to pcc2) of the pcc. (b) watchdog timer counting stops. caution do not execute the stop instruction while the subsystem clock is in operation.
125 chapter 7 clock generator users manual u10105ej4v1um00 7.6 changing system clock and cpu clock settings 7.6.1 time required for switchover between system clock and cpu clock the system clock and cpu clock can be switched over by means of bit 0 to bit 2 (pcc0 to pcc2) and bit 4 (css) of the processor clock control register (pcc). the actual switchover operation is not performed directly after writing to the pcc, but operation continues on the pre-switchover clock for several instructions (see table 7-2 ). determination as to whether the system is operating on the main system clock or the subsystem clock is performed by bit 5 (cls) of the pcc register. table 7-2. maximum time required for cpu clock switchover set values after switchover set values before switchover mcs css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 00000001001000110100 1xxx x 0 0 0 0 8 instructions 4 instructions 2 instructions 1 instruction 1 instruction 001 16 instructions 4 instructions 2 instructions 1 instruction 1 instruction 010 16 instructions 8 instructions 2 instructions 1 instruction 1 instruction 011 16 instructions 8 instructions 4 instructions 1 instruction 1 instruction 100 16 instructions 8 instructions 4 instructions 2 instructions 1 instruction 11 x x x f x /2f xt instruction f x /4f xt instruction f x /8f xt instruction f x /16f xt instruction f x /32f xt instruction (77 instructions) (39 instructions) (20 instructions) (10 instructions) (5 instructions) 0 f x /4f xt instruction f x /8f xt instruction f x /16f xt instruction f x /32f xt instruction f x /64f xt instruction (39 instructions) (20 instructions) (10 instructions) (5 instructions) (3 instructions) caution selection of the cpu clock cycle scaling factor (pcc0 to pcc2) and switchover from the main system clock to the subsystem clock (changing css from 0 to 1) should not be performed simultaneously. simultaneous setting is possible, however, for selection of the cpu clock cycle scaling factor (pcc0 to pcc2) and switchover from the subsystem clock to the main system clock (changing css from 1 to 0). remarks 1. one instruction is the minimum instruction execution time with the pre-switchover cpu clock. 2. figures in parentheses apply to operation with f x = 5.0 mhz and f xt = 32.768 khz.
126 chapter 7 clock generator users manual u10105ej4v1um00 v dd reset interrupt request signal system clock cpu clock wait (26.2 ms : 5.0 mhz) internal reset operation minimum speed operation maximum speed operation subsystem clock operation f xx f xx f xt f xx high-speed operation 7.6.2 system clock and cpu clock switching procedure this section describes switching procedure between system clock and cpu clock. figure 7-10. system clock and cpu clock switching (1) the cpu is reset by setting the reset signal to low level after power-on. after that, when reset is released by setting the reset signal to high level, main system clock starts oscillation. at this time, oscillation stabilization time (2 17 /f x ) is secured automatically. after that, the cpu starts executing the instruction at the minimum speed of the main system clock (12.8 m s when operated at 5.0 mhz). (2) after the lapse of a sufficient time for the v dd voltage to increase to enable operation at maximum speeds, the pcc and osms are rewritten and the maximum-speed operation is carried out. (3) upon detection of a decrease of the v dd voltage due to an interrupt, the main system clock is switched to the subsystem clock (which must be in an oscillation stable state). (4) upon detection of v dd voltage reset due to an interrupt, 0 is set to the mcc and oscillation of the main system clock is started. after the lapse of time required for stabilization of oscillation, the pcc and osms are rewritten and the maximum-speed operation is resumed. caution when subsystem clock is being operated while main system clock was stopped, if switching to the main system clock is made again, be sure to switch after securing oscillation stable time by software.
127 users manual u10105ej4v1um00 chapter 8 16-bit timer/event counter the timers incorporated into the m pd78064 and 78064y subseries are outlined below. (1) 16-bit timer/event counter (tm0) the tm0 can be used for an interval timer, pwm output, pulse widths measurement (infrared ray remote control receive function), external event counter, square wave output of any frequency or one-shot pulse output. (2) 8-bit timers/event counters 1 and 2 (tm1 and tm2) tm1 and tm2 can be used to serve as an interval timer and an external event counter and to output square waves with any selected frequency. two 8-bit timer/event counters can be used as one 16-bit timer/event counter (see chapter 9 8-bit timer/event counters 1 and 2 ). (3) watch timer (tm3) this timer can set a flag every 0.5 sec. and simultaneously generates interrupts at the preset time intervals (see chapter 10 watch timer ). (4) watchdog timer (wdtm) wdtm can perform the watchdog timer function or generate non-maskable interrupts, maskable interrupts and reset at the preset time intervals (see chapter 11 watchdog timer ). (5) clock output control circuit this circuit supplies other devices with the divided main system clock and the subsystem clock (see chapter 12 clock output control circuit ). (6) buzzer output control circuit this circuit outputs the buzzer frequency obtained by dividing the main system clock (see chapter 13 buzzer output control circuit ).
128 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 table 8-1. timer/event counter types and functions interval timer 2 channels note1 2 channels 1 channel note2 1 channel note3 external event counter ?? timer output ?? pwm output ? pulse width measurement ? square-wave output ?? one-shot pulse output ? interrupt request ???? test input ? notes 1. when capture/compare registers (cr00, cr01) are specified as compare registers. 2. tm3 can perform both watch timer and interval timer functions at the same time. 3. wdtm can perform either the watchdog timer function or the interval timer function. function type watch timer watchdog timer 16-bit timer/ 8-bit timer/event event counter counters 1 and 2
129 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 8.1 16-bit timer/event counter functions the 16-bit timer/event counter (tm0) has the following functions. ? interval timer ? pwm output ? pulse width measurement ? external event counter ? square-wave output ? one-shot pulse output (1) interval timer tm0 generates interrupts at the preset time interval. table 8-2. 16-bit timer/event counter interval times minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 ti00 input cycle 2 16 ti00 input cycle ti00 input edge cycle 2 1/f x 2 16 1/f x 1/f x (400 ns) (13.1 ms) (200 ns) 2 1/f x 2 2 1/f x 2 16 1/f x 2 17 1/f x 1/f x 2 1/f x (400 ns) (800 ns) (13.1 ms) (26.2 ms) (200 ns) (400 ns) 2 2 1/f x 2 3 1/f x 2 17 1/f x 2 18 1/f x 2 1/f x 2 2 1/f x (800 ns) (1.6 m s) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 3 1/f x 2 4 1/f x 2 18 1/f x 2 19 1/f x 2 2 1/f x 2 3 1/f x (1.6 m s) (3.2 m s) (52.4 ms) (104.9 ms) (800 ns) (1.6 m s) 2 watch timer output cycle 2 16 watch timer output cycle watch timer output edge cycle remarks 1. f x : main system clock oscillation frequency 2. mcs: oscillation mode selection register bit 0 3. values in parentheses when operated at f x = 5.0 mhz (2) pwm output tm0 can generate 14-bit resolution pwm output. (3) pulse width measurement tm0 can measure the pulse width of an externally input signal. (4) external event counter tm0 can measure the number of pulses of an externally input signal.
130 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 (5) square-wave output tm0 can output a square wave with any selected frequency. table 8-3. 16-bit timer/event counter square-wave output ranges minimum pulse width maximum pulse width resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 ti00 input cycle 2 16 ti00 input cycle ti00 input edge cycle 2 1/f x 2 16 1/f x 1/f x (400 ns) (13.1 ms) (200 ns) 2 1/f x 2 2 1/f x 2 16 1/f x 2 17 1/f x 1/f x 2 1/f x (400 ns) (800 ns) (13.1 ms) (26.2 ms) (200 ns) (400 ns) 2 2 1/f x 2 3 1/f x 2 17 1/f x 2 18 1/f x 2 1/f x 2 2 1/f x (800 ns) (1.6 m s) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 3 1/f x 2 4 1/f x 2 18 1/f x 2 19 1/f x 2 2 1/f x 2 3 1/f x (1.6 m s) (3.2 m s) (52.4 ms) (104.9 ms) (800 ns) (1.6 m s) 2 watch timer output cycle 2 16 watch timer output cycle watch timer output edge cycle remarks 1. f x : main system clock oscillation frequency 2. mcs: oscillation mode selection register bit 0 3. values in parentheses when operated at f x = 5.0 mhz (6) one-shot pulse output tm0 is able to output one-shot pulse which can set any width of output pulse.
131 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 8.2 16-bit timer/event counter configuration the 16-bit timer/event counter consists of the following hardware. table 8-4. 16-bit timer/event counter configuration item configuration timer register 16 bits 1 (tm0) register capture/compare register: 16 bits 2 (cr00, cr01) timer output 1 (to0) timer clock select register 0 (tcl0) 16-bit timer mode control register (tmc0) capture/compare control register 0 (crc0) control register 16-bit timer output control register (toc0) port mode register 3 (pm3) external interrupt mode register 0 (intm0) sampling clock select register (scs)
132 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 figure 8-1. 16-bit timer/event counter block diagram tcl06 tcl05 tcl04 timer clock selection register 0 3 internal bus capture/compare control register 0 crc02 crc01 crc00 selector ti01/ p01/intp1 inttm3 2f xx f xx f xx /2 f xx /2 2 selector 16-bit capture/compare control register (cr01) internal bus 16-bit capture/compare control register (cr00) clear match clear circuit tmc03 tmc02 tmc01 ovf0 ospt ospe toc04 lvs0 lvr0 toc01 toe0 16-bit timer mode control register 16-bit timer output control register 2 pwm pulse output controller 16-bit timer/event counter output control circuit note 2 tmc01-tmc03 intp0 inttm01 to0/p30 intp1 inttm00 match tmc01-tmc03 3 16-bit timer register (tm0) ti00/p00/ intp0 note 1 crc02 notes 1. edge detection circuit 2. the configuration of the 16-bit timer/event counter output control circuit is shown in figure 8-2.
133 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 figure 8-2. 16-bit timer/event counter output control circuit block diagram remark the circuitry enclosed by the dotted line is the output control circuit. pwm pulse output control circuit edge detection circuit ti00/p00/ intp0 ospt 16-bit timer output control register ospe toc04 lvs0 lvr0 toc01 toe0 selector selector inv s r q 3 level inversion crc02 inttm01 crc00 inttm00 one-shot pulse output control circuit 2 es11 es10 external interrupt mode register 0 16-bit timer mode control register tmc03 tmc02 tmc01 p30 output latch pm30 port mode register 3 to0/p30 internal bus
134 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 (1) capture/compare register 00 (cr00) cr00 is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or as a compare register is set by bit 0 (crc00) of capture/compare control register 0. when cr00 is used as a compare register, the value set in the cr00 is constantly compared with the 16- bit timer register (tm0) count value, and an interrupt request (inttm00) is generated if they match. it can also be used as the register which holds the interval time when tm0 is set to interval timer operation, and as the register which sets the pulse width in the pwm operating mode. when cr00 is used as a capture register, it is possible to select the valid edge of the intp0/ti00 pin or the intp1/ti01 pin as the capture trigger. setting of the intp0/ti00 or intp1/ti01 valid edge is performed by means of external interrupt mode register 0. if cr00 is specified as a capture register and capture trigger is specified to be the valid edge of the intp0/ ti00 pin, the situation is as shown in the following table. table 8-5. intp0/ti00 pin valid edge and cr00 capture trigger valid edge es11 es10 intp0/ti00 pin valid edge cr00 capture trigger valid edge 0 0 falling edge rising edge 0 1 rising edge falling edge 1 0 setting prohibited 1 1 both rising and falling edges no capture operation cr00 is set by a 16-bit memory manipulation instruction. after reset input, the value of cr00 is undefined. (2) capture/compare register 01 (cr01) cr01 is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or a compare register is set by bit 2 (crc02) of capture/compare control register 0. when cr01 is used as a compare register, the value set in the cr01 is constantly compared with the 16- bit timer register (tm0) count value, and an interrupt request (inttm01) is generated if they match. when cr01 is used as a capture register, it is possible to select the valid edge of the intp0/ti00 pin as the capture trigger. setting of the intp0/ti00 valid edge is performed by means of external interrupt mode register 0. cr01 is set with a 16-bit memory manipulation instruction. after reset input, the value of cr01 is undefined. (3) 16-bit timer register (tm0) tm0 is a 16-bit register which counts the count pulses. tm0 is read by a 16-bit memory manipulation instruction. when tm0 is read, capture/compare register (cr01) should first be set as a capture register. reset input sets tm0 to 0000h. caution as reading of the value of tm0 is performed via cr01, the previously set value of cr01 is lost.
135 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 8.3 16-bit timer/event counter control registers the following seven types of registers are used to control the 16-bit timer/event counter. ? timer clock select register 0 (tcl0) ? 16-bit timer mode control register (tmc0) ? capture/compare control register 0 (crc0) ? 16-bit timer output control register (toc0) ? port mode register 3 (pm3) ? external interrupt mode register 0 (intm0) ? sampling clock select register (scs) (1) timer clock select register 0 (tcl0) this register is used to set the count clock of the 16-bit timer register. tcl0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tcl0 value to 00h. remark tcl0 has the function of setting the pcl output clock in addition to that of setting the count clock of the 16-bit timer register. cautions 1. setting of the ti00/intp0 pin valid edge is performed by external interrupt mode register 0, and selection of the sampling clock frequency is performed by the sampling clock selection register. 2. when enabling pcl output, set tcl00 to tcl03, then set 1 in cloe with a 1-bit memory manipulation instruction. 3. to read the count value when ti00 has been specified as the tm0 count clock, the value should be read from tm0, not from capture/compare register 01 (cr01). 4. when rewriting tcl0 to other data, stop the timer operation beforehand.
136 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 figure 8-3. timer clock selection register 0 format cloe tcl06 tcl05 tcl04 tcl03 tcl02 tcl01 tcl00 76543210 symbol tcl0 tcl03 tcl02 tcl01 tcl00 0000f xt (32.768 khz) 0101f xx f x (5.0 mhz) f x /2 (2.5 mhz) 0110f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 0111f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 1000f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 1001f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 1010f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 1011f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 1100f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) mcs=1 pcl output clock selection mcs=0 ff40h 00h r/w address after reset r/w other than above setting prohibited tcl06 tcl05 tcl04 0 0 0 ti00 (valid edge specifiable) 0012f xx setting prohibited f x (5.0 mhz) 010f xx f x (5.0 mhz) f x /2 (2.5 mhz) 011f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 100f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 1 1 1 watch timer output (inttm 3) mcs=1 16-bit timer register count clock selection mcs=0 other than above setting prohibited cloe 1 output enabled pcl output control 0 output disabled remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. ti00 : 16-bit timer/event counter input pin 5. tm0 : 16-bit timer register 6. mcs : bit 0 of oscillation mode selection register 7. figures in parentheses apply to operation with f x = 5.0 mhz of f xt = 32.768 khz.
137 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 (2) 16-bit timer mode control register (tmc0) this register sets the 16-bit timer operating mode, the 16-bit timer register clear mode and output timing, and detects an overflow. tmc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc0 value to 00h. caution the 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation stop mode) is set in tmc01 to tmc03, respectively. set 0, 0, 0 in tmc01 to tmc03 to stop the operation.
138 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 figure 8-4. 16-bit timer mode control register format 0000 tmc03 tmc02 tmc01 ovf0 76543210 symbol tmc0 ff48h 00h r/w address after reset r/w ovf0 16-bit timer register overflow detection 0 overflow not detected 1 overflow detected tmc03 tmc02 tmc01 operating mode clear mode selection to0 output timing selection interrupt generation 000 operation stop (tm0 cleared to 0) no change not generated 001 pwm mode (free running) pwm pulse output 010 011 100 101 110 111 free running mode match between tm0 and cr00 or match between tm0 and cr01 match between tm0 and cr00, match between tm0 and cr01 or ti00 valid edge match between tm0 and cr00 or match between tm0 and cr01 match between tm0 and cr00, match between tm0 and cr01 or ti00 valid edge match between tm0 and cr00 or match between tm0 and cr01 match between tm0 and cr00, match between tm0 and cr01 or ti00 valid edge clear & start on ti00 valid edge clear & start on match between tm0 and cr00 generated on match between tm0 and cr00, and match between tm0 and cr01 remark to0 : 16-bit timer/event counter output pin ti00 : 16-bit timer/event counter input pin tm0 : 16-bit timer register cr00 : compare register 00 cr01 : compare register 01 cautions 1. switch the clear mode and the t00 output timing after stopping the timer operation (by setting tmc01 to tmc03 to 0, 0, 0). 2. set the valid edge of the ti00/intp0 pin with an external interrupt mode register 0 and select the sampling clock frequency with a sampling clock select register. 3. when using the pwm mode, set the pwm mode and then set data to cr00. 4. if clear & start mode on match between tm0 and cr00 is selected, when the set value of cr00 is ffffh and the tm0 value changes from ffffh to 0000h, ovf0 flag is set to 1.
139 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 0000 0 crc02 crc01 crc00 76543210 symbol crc0 ff4ch 04h r/w address after reset r/w crc00 cr00 operating mode selection 0 operates as compare register 1 operates as capture register crc01 cr00 capture trigger selection captures on valid edge of ti01 captures on valid edge of ti00 0 1 crc02 cr01 operating mode selection operates as compare register operates as capture register 0 1 (3) capture/compare control register 0 (crc0) this register controls the operation of the capture/compare registers (cr00, cr01). crc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets crc0 value to 04h. figure 8-5. capture/compare control register 0 format cautions 1. timer operation must be stopped before setting crc0. 2. when clear & start mode on a match between tm0 and cr00 is selected with the 16- bit timer mode control register, cr00 should not be specified as a capture register.
140 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 (4) 16-bit timer output control register (toc0) this register controls the operation of the 16-bit timer/event counter output control circuit. it sets r-s type flip-flop (lv0) setting/resetting, the active level in pwm mode, inversion enabling/disabling in modes other than pwm mode, 16-bit timer/event counter timer output enabling/disabling, one-shot pulse output operation enabling/disabling, and output trigger for a one-shop pulse by software. toc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets toc0 value to 00h. cautions 1. timer operation must be stopped before setting toc0. 2. if lvs0 and lvr0 are read after data is set, they will be 0. 3. ospt is cleared automatically after data setting, and will therefore be 0 if read. figure 8-6. 16-bit timer output control register format 0 ospt ospe toc04 lvs0 lvr0 toc01 toe0 76543210 symbol toc0 ff4eh 00h r/w address after reset r/w toe0 16-bit timer/event counter output control 0 output disabled (port mode) 1 output enabled toc01 0 1 in pwm mode in other modes active level selection timer output f/f control by match of cr00 and tm0 active high active low inversion operation disabled inversion operation enabled lvs0 lvr0 16-bit timer/event counter timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc04 timer output f/f control by match of cr01 and tm0 0 inversion operation disabled 1 inversion operation enabled ospe one-shot pulse output control 0 continuous pulse output 1 one-shot pulse output ospt control of one-shot pulse output trigger by software 0 one-shot pulse trigger not used 1 one -shot pulse trigger used
141 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 (5) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p30/to0 pin for timer output, set pm30 and output latch of p30 to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 value to ffh. figure 8-7. port mode register 3 format pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 76543210 symbol pm3 ff23h ffh r/w address after reset r/w pm3n p3n pin input/output mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off)
142 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 (6) external interrupt mode register 0 (intm0) this register is used to set intp0 to intp2 valid edges. intm0 is set with an 8-bit memory manipulation instruction. reset input sets intm0 value to 00h. figure 8-8. external interrupt mode register 0 format es31 es30 es21 es20 es11 es10 0 0 76543210 symbol intm0 ffech 00h r/w address after reset r/w es11 intp0 valid edge selection es10 0 falling edge 0 0 rising edge 1 1 setting prohibited 0 1 both falling and rising edges 1 es21 intp1 valid edge selection es20 0 falling edge 0 0 rising edge 1 1 setting prohibited 0 1 both falling and rising edges 1 es31 intp2 valid edge selection es30 0 falling edge 0 0 rising edge 1 1 setting prohibited 0 1 both falling and rising edges 1
143 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 (7) sampling clock select registers (scs) this register sets clocks which undergo clock sampling of valid edges to be input to intp0. when remote controlled reception is carried out using intp0, digital noise is removed with sampling clock. scs is set with an 8-bit memory manipulation instruction. reset input sets scs value to 00h. figure 8-9. sampling clock select register format 0 0 0 0 0 0 scs1 scs0 76543210 symbol scs ff47h 00h r/w address after reset r/w scs1 scs0 00 01 10 11 intp0 sampling clock selection mcs=1 mcs=0 f xx /2 n f x /2 7 (39.1 khz) f xx /2 7 f x /2 8 (19.5 khz) f x /2 5 (156.3 khz) f xx /2 5 f x /2 6 (78.1 khz) f x /2 6 (78.1 khz) f xx /2 6 f x /2 7 (39.1 khz) caution f xx /2 n is the clock supplied to the cpu, and f xx /2 5 , f xx /2 6 , and f xx /2 7 are clocks supplied to peripheral hardware. f xx /2 n is stopped in halt mode. remarks 1. n : value set in bit 0 to bit 2 (pcc0 to pcc2) of the processor clock control register (n = 0 to 4) 2. f xx : main system clock frequency (f x or f x /2) 3. f x : main system clock oscillation frequency 4. mcs : bit 0 of oscillation mode selection register 5. figures in parentheses apply to operation with f x = 5.0 mhz.
144 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 8.4 16-bit timer/event counter operations 8.4.1 interval timer operations setting the 16-bit timer mode control register (tmc0) and capture/compare control register 0 (crc0) as shown in figure 8-10 allows operation as an interval timer. interrupts are generated repeatedly using the count value set in 16-bit capture/compare register 00 (cr00) beforehand as the interval. when the count value of the 16-bit timer register (tm0) matches the value set to cr00, counting continues with the tm0 value cleared to 0 and the interrupt request signal (inttm00) is generated. count clock of the 16-bit timer/event counter can be selected with bit 4 to bit 6 (tcl04 to tcl06) of the timer clock select register 0 (tcl0). figure 8-10. control register settings for interval timer operation (a) 16-bit timer mode control register (tmc0) 0000110/10 tmc03 tmc02 tmc01 ovf0 tmc0 clear & start on match tm0 and cr00 (b) capture/compare control register 0 (crc0) 0 0 0 0 0 0/1 0/1 0 crc02 crc01 crc00 crc0 cr00 set as compare register remark 0/1 : setting 0 or 1 allows another function to be used simultaneously with the interval timer. see the description of the respective control registers for details.
145 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 figure 8-11. interval timer configuration diagram 16-bit capture/compare register 00 (cr00) 16-bit timer register (tm0) selector f xx /2 2 f xx /2 f xx 2f xx inttm3 ti00/p00/intp0 ovf0 clear circuit inttm00 figure 8-12. interval timer operation timings t count clock tm0 count value cr00 inttm00 to0 interval time interval time interval time 0000 0001 n 0000 0001 n 0000 0001 n count start clear clear nn nn interrupt acknowledge interrupt acknowledge remark interval time = (n + 1) t : n = 0001h to ffffh.
146 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 table 8-6. 16-bit timer/event counter interval times minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 000 2 ti00 input cycle 2 16 ti00 input cycle ti00 input edge cycle 0 0 1 setting 2 1/f x setting 2 16 1/f x setting 1/f x prohibited (400 ns) prohibited (13.1 ms) prohibited (200 ns) 0102 1/f x 2 2 1/f x 2 16 1/f x 2 17 1/f x 1/f x 2 1/f x (400 ns) (800 ns) (13.1 ms) (26.2 ms) (200 ns) (400 ns) 0112 2 1/f x 2 3 1/f x 2 17 1/f x 2 18 1/f x 2 1/f x 2 2 1/f x (800 ns) (1.6 m s) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 1002 3 1/f x 2 4 1/f x 2 18 1/f x 2 19 1/f x 2 2 1/f x 2 3 1/f x (1.6 m s) (3.2 m s) (52.4 ms) (104.9 ms) (800 ns) (1.6 m s) 1112 watch timer output cycle 2 16 watch timer output cycle watch timer output edge cycle other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register 3. figures in parentheses apply to operation with f x = 5.0 mhz 8.4.2 pwm output operations setting the 16-bit timer mode control register (tmc0), capture/compare control register 0 (crc0), and the 16-bit timer output control register (toc0) as shown in figure 8-13 allows operation as pwm output. pulses with the duty rate determined by the value set in 16-bit capture/compare register 00 (cr00) beforehand are output from the to0/ p30 pin. set the active level width of the pwm pulse to the high-order 14 bits of cr00. select the active level with bit 1 (toc01) of the 16- bit timer output control register (toc0). this pwm pulse has a 14-bit resolution. the pulse can be converted to an analog voltage by integrating it with an external low-pass filter (lpf). the pwm pulse is formed by a combination of the basic cycle determined by 2 8 / f and the sub-cycle determined by 2 14 / f so that the time constant of the external lpf can be shortened. count clock f can be selected with bit 4 to bit 6 (tcl04 to tcl06) of the timer clock select register 0 (tcl0). pwm output enable/disable can be selected with bit 0 (toe0) of toc0. cautions 1. pwm operation mode should be selected before setting cr00. 2. be sure to write 0 to bits 0 and 1 of cr00. 3. do not select pwm operation mode for external clock input from the ti00/p00 pin. tcl06 tcl05 tcl04
147 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 figure 8-13. control register settings for pwm output operation (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) tmc0 0 1 0 0 0 0 0 0 ovf0 tmc01 tmc02 tmc03 pwm mode crc00 crc01 crc02 crc0 0 0/1 0/1 0 0 0 0 0 cr00 set as com p are re g ister toe0 toc01 lvr0 lvs0 toc04 ospe ospt toc0 1 0/1 0 to0 output enabled s p ecifies active level remarks 1. 0/1 : setting 0 or 1 allows another function to be used simultaneously with pwm output. see the description of the respective control registers for details. 2. : don't care
148 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 by integrating 14-bit resolution pwm pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and d/a converter applications, etc. the analog output voltage (v an ) used for d/a conversion with the configuration shown in figure 8-14 is as follows. v an = v ref 2 16 v ref : external switching circuit reference voltage figure 8-14. example of d/a converter configuration with pwm output capture/compare register 00 (cr00) value figure 8-15 shows an example in which pwm output is converted to an analog voltage and used in a voltage synthesizer type tv tuner. figure 8-15. tv tuner application circuit example switching circuit to0/p30 pwm signal v ref low-pass filter analog output (v an ) pd78064, 78064y m pd78064, 78064y m to0/p30 v ss 8.2 k w 8.2 k w 100 pf 22 k w +110 v 2sc 2352 47 k w 47 k w 47 k w 0.22 f m 0.22 f m 0.22 f m electronic tuner gnd pc574j m
149 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 8.4.3 ppg output operations setting the 16-bit timer mode control register (tmc0) and capture/compare control register 0 (crc0) as shown in figure 8-16 allows operation as ppg (programmable pulse generator) output. in the ppg output operation, square waves are output from the to0/p30 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16-bit capture/compare register 01 (cr01) and in 16-bit capture/ compare register 00 (cr00), respectively. figure 8-16. control register settings for ppg output operation (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) tmc0 0 0 1 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start on match of tm0 and cr00 crc0 0 0 0 0 0 0 0 crc00 crc01 crc02 cr00 set as compare register cr01 set as com p are re g ister (c) 16-bit timer output control register (toc0) toc0 1 1 0/1 0/1 1 0 0 0 toe0 toc01 lvr0 lvs0 ospt ospe toc04 to0 output enabled inversion of output on match of tm0 and cr00 specified to0 output f/f initial value inversion of output on match of tm0 and cr01 one-shot p ulse out p ut disabled caution values in the following range should be set in cr00 and cr01: 0000h cr01 < cr00 ffffh remark : don't care
150 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 8.4.4 pulse width measurement operations it is possible to measure the pulse width of the signals input to the ti00/p00 pin and ti01/p01 pin using the 16-bit timer register (tm0). there are two measurement methods: measuring with tm0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the ti00/p00 pin. (1) pulse width measurement with free-running counter and one capture register when the 16-bit timer register (tm0) is operated in free-running mode (see register settings in figure 8-17), and the edge specified by external interrupt mode register 0 (intm0) is input to the ti00/p00 pin, the value of tm0 is taken into 16-bit capture/compare register 01 (cr01) and an external interrupt request signal (intp0) is set. any of three edge specifications can be selectedrising, falling, or both edgesby means of bits 2 and 3 (es10 and es11) of intm0. for valid edge detection, sampling is performed at the interval selected by means of the sampling clock selection register (scs), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 8-17. control register settings for pulse width measurement with free-running counter and one capture register (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) tmc0 0 0/1 1 0 0 0 0 0 ovf0 tmc01 tmc02 tmc03 free-runnin g mode remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measure- ment. see the description of the respective control registers for details. crc0 0 0/1 1 0 0 0 0 0 crc00 crc01 crc02 cr00 set as compare register cr01 set as capture register
151 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 figure 8-18. configuration diagram for pulse width measurement by free-running counter selector f xx /2 2 f xx /2 f xx 2f xx inttm3 16-bit timer register (tm0) 16-bit capture/compare register 01 (cr01) ovf0 intp0 internal bus ti00/p00/intp00 figure 8-19. timing of pulse width measurement operation by free-running counter and one capture register (with both edges specified) count clock tm0 count value ti00 pin input cr01 captured value intp0 ovf0 0000 0001 d0 d1 ffff 0000 d2 d3 d0 d1 d2 d3 (d1 ?d0) t (10000h ?d1 + d2) t (d3 ?d2) t t
152 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 (2) measurement of two pulse widths with free-running counter when the 16-bit timer register (tm0) is operated in free-running mode (see register settings in figure 8-20), it is possible to simultaneously measure the pulse widths of the two signals input to the ti00/p00 pin and the ti01/p01 pin. when the edge specified by bits 2 and 3 (es10 and es11) of external interrupt mode register 0 (intm0) is input to the ti00/p00 pin, the value of tm0 is taken into 16-bit capture/compare register 01 (cr01) and an external interrupt request signal (intp0) is set. also, when the edge specified by bits 4 and 5 (es20 and es21) of intm0 is input to the ti01/p01 pin, the value of tm0 is taken into 16-bit capture/compare register 00 (cr00) and an external interrupt request signal (intp1) is set. any of three edge specifications can be selectedrising, falling, or both edgesas the valid edges for the ti00/p00 pin and the ti01/p01 pin by means of bits 2 and 3 (es10 and es11) and bits 4 and 5 (es20 and es21) of intm0, respectively. for ti00/p00 pin valid edge detection, sampling is performed at the interval selected by means of the sampling clock selection register (scs), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 8-20. control register settings for two pulse width measurements with free-running counter (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) tmc0 0 0/1 1 0 0 0 0 0 ovf0 tmc01 tmc02 tmc03 free-running mode crc0 1 0 1 0 0 0 0 0 crc00 crc01 crc02 cr00 set as capture register captured in cr00 on valid edge of ti01/p01 pin cr01 set as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measure- ment. see the description of the respective control registers for details.
153 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 figure 8-21. timing of pulse width measurement operation with free-running counter (with both edges specified) count clock tm0 count value ti00 pin input cr01 captured value intp0 ti01 pin input t cr00 captured value intp1 ovf0 (d1 ?d0) t (10000h ?d1 + d2) t (10000h ?d1 + (d2 + 1)) t (d3 ?d2) t 0000 0001 d0 d1 0000 d3 d2 ffff d0 d1 d3 d2 d1
154 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 (3) pulse width measurement with free-running counter and two capture registers when the 16-bit timer register (tm0) is operated in free-running mode (see register settings in figure 8-22), it is possible to measure the pulse width of the signal input to the ti00/p00 pin. when the edge specified by bits 2 and 3 (es10 and es11) of external interrupt mode register 0 (intm0) is input to the ti00/p00 pin, the value of tm0 is taken into 16-bit capture/compare register 01 (cr01) and an external interrupt request signal (intp0) is set. also, on the inverse edge input of that of the capture operation into cr01, the value of tm0 is taken into 16-bit capture/compare register 00 (cr00). either of two edge specifications can be selectedrising or fallingas the valid edges for the ti00/p00 pin by means of bits 2 and 3 (es10 and es11) of intm0. for ti00/p00 pin valid edge detection, sampling is performed at the interval selected by means of the sampling clock selection register (scs), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. caution if the valid edge of ti00/p00 is specified to be both rising and falling edge, capture/compare register 00 (cr00) cannot perform the capture operation. figure 8-22. control register settings for pulse width measurement with free-running counter and two capture registers (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) tmc0 0 0/1 1 0 0 0 0 0 ovf0 tmc01 tmc02 tmc03 free-running mode crc0 1 1 1 0 0 0 0 0 crc00 crc01 crc02 cr00 set as capture register captured in cr00 on invalid edge of ti00/p00 pin cr01 set as capture register remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measure- ment. see the description of the respective control registers for details.
155 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 figure 8-23. timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) count clock tm0 count value ti00 pin input cr01 captured value cr00 captured value intp0 ovf0 (d1-d0) t (10000h-d1 + d2) t (d3-d2) t d1 d3 d0 d2 d3 d2 0000 ffff d1 d0 0000 0001 t
156 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 (4) pulse width measurement by means of restart when input of a valid edge to the ti00/p00 pin is detected, the count value of the 16-bit timer register (tm0) is taken into 16-bit capture/compare register 01 (cr01), and then the pulse width of the signal input to the ti00/p00 pin is measured by clearing tm0 and restarting the count (see register settings in figure 8-24). the edge specification can be selected from two types, rising and falling edges by intm0 bits 2 and 3 (es10 and es11). in a valid edge detection, the sampling is performed by a cycle selected by the sampling clock selection register (scs), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. caution if the valid edge of ti00/p00 is specified to be both rising and falling edge, the 16-bit capture/ compare register 00 (cr00) cannot perform the capture operation. figure 8-24. control register settings for pulse width measurement by means of restart (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measure- ment. see the description of the respective control registers for details. figure 8-25. timing of pulse width measurement operation by means of restart (with rising edge specified) count clock tm0 count value ti00 pin input cr01 captured value cr00 captured value intp0 t 0000 0001 d0 0000 0001 d1 0001 0000 d2 d0 d2 d1 d1 t d2 t tmc0 0 0/1 0 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start with valid edge of ti00/p00 pin crc0 1 1 1 0 0 0 0 0 crc00 crc01 crc02 cr00 set as capture register captured in cr00 on invalid edge of ti00/p00 pin cr01 set as capture register
157 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 8.4.5 external event counter operation the external event counter counts the number of external clock pulses to be input to the ti00/p00 pin with the 16-bit timer register (tm0). tm0 is incremented each time the valid edge specified with the external interrupt mode register 0 (intm0) is input. when the tm0 counted value matches the 16-bit capture/compare register 00 (cr00) value, tm0 is cleared to 0 and the interrupt request signal (inttm00) is generated. the rising edge, the falling edge or both edges can be selected with bits 2 and 3 (es10 and es11) of intm0. because operation is carried out only after the valid edge is detected twice by sampling at the interval selected with the sampling clock select register (scs), noise with short pulse widths can be removed. figure 8-26. control register settings in external event counter mode (a) 16-bit timer mode control register (tmc0) tmc0 0 0/1 1 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start with match of tm0 and cr00 crc0 0 0/1 0/1 0 0 0 0 0 crc00 crc01 crc02 cr00 set as com p are re g ister (b) capture/compare control register 0 (crc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the external event counter. see the description of the respective control registers for details.
158 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 figure 8-27. external event counter configuration diagram 16-bit capture/compare register 00 (cr00) clear inttm00 intp0 16-bit timer register (tm0) 16-bit capture/compare register 01 (cr01) internal bus ti00 valid edge ovf0 figure 8-28. external event counter operation timings (with rising edge specified) ti00 pin input tm0 count value cr00 inttm0 n 0000 0001 0002 0003 0004 0005 n-1 n 0000 0001 0002 0003 caution when reading the external event counter count value, tm0 should be read.
159 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 8.4.6 square-wave output operation a square wave with any selected frequency is output at intervals of the count value preset to the 16-bit capture/ compare register 00 (cr00). the to0/p30 pin output status is reversed at intervals of the count value preset to cr00 by setting bit 0 (toe0) and bit 1 (toc01) of the 16-bit timer output control register to 1. this enables a square wave with any selected frequency to be output. figure 8-29. control register settings in square-wave output mode (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with square-wave output. see the description of the respective control registers for details. crc0 0 0/1 0/1 0 0 0 0 0 crc00 crc01 crc02 cr00 set as compare register tmc0 0 0/1 1 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start on match of tm0 and cr00 toc0 1 1 0/1 0/1 0 0 0 0 toe0 toc01 lvr0 ospt ospe toc04 lvs0 to0 output enabled inversion of output on match of tm0 and cr00 specified to0 output f/f initial value no inversion of output on match of tm0 and cr01 one-shot pulse output disabled
160 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 ti00 pin input tm0 count value cr00 inttm0 to0 pin output 0000 0001 0002 n-1 n 0000 0001 0002 n-1 n 0000 n figure 8-30. square-wave output operation timing table 8-7. 16-bit timer/event count square-wave output ranges minimum pulse width maximum pulse width resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 ti00 input cycle 2 16 ti00 input cycle ti00 input edge cycle 2 1/f x 2 16 1/f x 1/f x (400 ns) (13.1 ms) (200 ns) 2 1/f x 2 2 1/f x 2 16 1/f x 2 17 1/f x 1/f x 2 1/f x (400 ns) (800 ns) (13.1 ms) (26.2 ms) (200 ns) (400 ns) 2 2 1/f x 2 3 1/f x 2 17 1/f x 2 18 1/f x 2 1/f x 2 2 1/f x (800 ns) (1.6 m s) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 3 1/f x 2 4 1/f x 2 18 1/f x 2 19 1/f x 2 2 1/f x 2 3 1/f x (1.6 m s) (3.2 m s) (52.4 ms) (104.9 ms) (800 ns) (1.6 m s) 2 watch timer output cycle 2 16 watch timer output cycle watch timer output edge cycle remarks 1. f x : main system clock oscillation frequency 2. mcs : oscillation mode selection register bit 0 3. values in parentheses when operated at f x = 5.0 mhz
161 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 8.4.7 one-shot pulse output operation it is possible to output one-shot pulses synchronized with a software trigger or an external trigger (ti00/p00 pin input). (1) one-shot pulse output using software trigger if the 16-bit timer mode control register (tmc0), capture/compare control register 0 (crc0), and the 16-bit timer output control register (toc0) are set as shown in figure 8-31, and 1 is set in bit 6 (ospt) of toc0 by software, a one-shot pulse is output from the to0/p30 pin. by setting 1 in ospt, the 16-bit timer/event counter is cleared and started, and output is activated by the count value set beforehand in 16-bit capture/compare register 01 (cr01). thereafter, output is inactivated by the count value set beforehand in 16-bit capture/compare register 00 (cr00). tm0 continues to operate after one-shot pulse is output. to stop tm0, 00h must be set to tmc0. caution when outputting one-shot pulse, do not set 1 in ospt. when outputting one-shot pulse again, execute after the inttm00, or interrupt match signal with cr00, is generated. figure 8-31. control register settings for one-shot pulse output operation using software trigger (a) 16-bit timer mode control register (tmc0) tmc0 0 0 1 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start with match of tm0 and cr00 crc0 0 0/1 0 0 0 0 0 0 crc00 crc01 crc02 cr00 set as compare register cr01 set as compare register (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) toc0 1 1 0/1 0/1 1 1 0 0 toe0 toc01 lvr0 ospt ospe toc04 lvs0 to0 output enabled inversion of output on match of tm0 and cr00 specified to0 output f/f initial value inversion of output on match of tm0 and cr01 one-shot pulse output mode set 1 in case of output caution values in the following range should be set in cr00 and cr01. 0000h cr01 < cr00 ffffh remark 0/1: setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output. see the description of the respective control registers for details.
162 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 figure 8-32. timing of one-shot pulse output operation using software trigger caution the 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation stop mode) is set to tmc01 to tmc03, respectively. count clock tm0 count value cr01 set value cr00 set value inttm01 ospt inttm00 to0 pin output 0000 0001 n n+1 0000 n-1 n m-1 m 0000 0001 0002 n m n m n m n m set 0ch to tmc0 (tm0 count start)
163 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 (2) one-shot pulse output using external trigger if the 16-bit timer mode control register (tmc0), capture/compare control register 0 (crc0), and the 16-bit timer output control register (toc0) are set as shown in figure 8-33, a one-shot pulse is output from the to0/ p30 pin with a ti00/p00 valid edge as an external trigger. any of three edge specifications can be selectedrising, falling, or both edges as the valid edges for the ti00/p00 pin by means of bits 2 and 3 (es10 and es11) of external interrupt mode register 0 (intm0). when a valid edge is input to the ti00/p00 pin, the 16-bit timer/event counter is cleared and started, and output is activated by the count values set beforehand in 16-bit capture/compare register 01 (cr01). thereafter, output is inactivated by the count value set beforehand in 16-bit capture/compare register 00 (cr00). caution when outputting one-shot pulses, external trigger is ignored if generated again. figure 8-33. control register settings for one-shot pulse output operation using external trigger (a) 16-bit timer mode control register (tmc0) toc0 1 1 0/1 0/1 1 1 0 0 toe0 toc01 lvr0 lvs0 ospt ospe toc04 to0 output enabled inversion of output on match of tm0 and cr00 specified to0 output f/f initial value inversion of output on match of tm0 and cr01 one-shot p ulse out p ut mode crc0 0 0/1 0 0 0 0 0 0 crc00 crc01 crc02 cr00 set as compare register cr01 set as com p are re g ister (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) caution values in the following range should be set in cr00 and cr01. 0000h cr01 < cr00 ffffh remark 0/1: setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output. see the description of the respective control registers for details. tmc0 0 0 0 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start with valid edge of ti00/p00 pin
164 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 figure 8-34. timing of one-shot pulse output operation using external trigger (with rising edge specified) caution the 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation stop mode) is set to tmc01 to tmc03, respectively. count clock tm0 count value cr01 set value cr00 set value inttm01 ti00 pin input inttm00 to0 pin output 0000 0001 0000 n n+1 n+2 m? m? m m+1 m+2 m+3 n m n m n m n m set 08h to tmc0 (tm0 count start)
165 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 8.5 16-bit timer/event counter operating precautions (1) timer start errors an error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. this is because the 16-bit timer register (tm0) is started asynchronously with the count pulse. figure 8-35. 16-bit timer register start timing timer start count pulse tm0 count value 0000h 0001h 0002h 0003h 0004h (2) 16-bit compare register setting set a value other than 0000h to the 16-bit capture/compare register 00 (cr00). thus, when using the 16-bit capture/compare register as event counter, one-pulse count operation cannot be carried out. (3) operation after compare register change during timer count operation if the value after the 16-bit capture/compare register (cr00) is changed is smaller than that of the 16-bit timer register (tm0), tm0 continues counting, overflows and then restarts counting from 0. thus, if the value (m) after cr00 change is smaller than that (n) before change, it is necessary to restart the timer after changing cr00. figure 8-36. timings after change of compare register during timer count operation remark n > x > m count pulse cr00 tm0 count value x-1 x ffffh 0000h 0001h 0002h m n
166 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 (4) capture register data retention timings if the valid edge of the ti00/p00 pin is input during 16-bit capture/compare register 01 (cr01) read, cr01 holds data without carrying out capture operation. however, the interrupt request flag (pif0) is set upon detection of the valid edge. figure 8-37. capture register data retention timing (5) valid edge setting set the valid edge of the ti00/intp0 pin after setting bits 1 to 3 (tmc01 to tmc03) of the 16-bit timer mode control register to 0, 0 and 0, respectively, and then stopping timer operation. valid edge setting is carried out with bits 2 and 3 (es10 and es11) of the external interrupt mode register 0. (6) re-trigger of one-shot pulse (a) one-shot pulse output using software when outputting one-shot pulse, do not set 1 in ospt. when outputting one-shot pulse again, execute it after the inttm00, or interrupt match signal with cr00, is generated. (b) one-shot pulse output using external trigger when outputting one-shot pulses, external trigger is ignored if generated again. count pulse tm0 count value edge input interrupt request flag capture read signal cr01 captured value capture operation i g nored x n+1 n n+1 n+2 m m+1 m+2
167 chapter 8 16-bit timer/event counter users manual u10105ej4v1um00 count pulse cr00 tm0 ovf0 inttm00 ffffh fffeh ffffh 0000h 0001h (7) operation of ovf0 flag ofv0 flag is set to 1 in the following case. the clear & start mode on match between tm0 and cr00 is selected. cr00 is set to ffffh. when tm0 is counted up from ffffh to 0000h. figure 8-38. operation timing of ovf0 flag
168 users manual u10105ej4v1um00 [memo]
169 users manual u10105ej4v1um00 chapter 9 8-bit timer/event counters 1 and 2 9.1 8-bit timer/event counters 1 and 2 functions for the 8-bit timer/event counters 1 and 2, two modes are available. one is a mode for two-channel 8-bit timer/ event counters to be used separately (the 8-bit timer/event counter mode) and the other is a mode for the 8-bit timer/ event counter to be used as 16-bit timer/event counter (the 16-bit timer/event counter mode). 9.1.1 8-bit timer/event counter mode the 8-bit timer/event counters 1 and 2 (tm1 and tm2) have the following functions. ? interval timer ? external event counter ? square-wave output
170 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 (1) 8-bit interval timer interrupts are generated at the preset time intervals. table 9-1. 8-bit timer/event counters 1 and 2 interval times minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 1/f x 2 2 1/f x 2 9 1/f x 2 10 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (102.4 m s) (204.8 m s) (400 ns) (800 ns) 2 2 1/f x 2 3 1/f x 2 10 1/f x 2 11 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 m s) (204.8 m s) (409.6 m s) (800 ns) (1.6 m s) 2 3 1/f x 2 4 1/f x 2 11 1/f x 2 12 1/f x 2 3 1/f x 2 4 1/f x (1.6 m s) (3.2 m s) (409.6 m s) (819.2 m s) (1.6 m s) (3.2 m s) 2 4 1/f x 2 5 1/f x 2 12 1/f x 2 13 1/f x 2 4 1/f x 2 5 1/f x (3.2 m s) (6.4 m s) (819.2 m s) (1.64 ms) (3.2 m s) (6.4 m s) 2 5 1/f x 2 6 1/f x 2 13 1/f x 2 14 1/f x 2 5 1/f x 2 6 1/f x (6.4 m s) (12.8 m s) (1.64 ms) (3.28 ms) (6.4 m s) (12.8 m s) 2 6 1/f x 2 7 1/f x 2 14 1/f x 2 15 1/f x 2 6 1/f x 2 7 1/f x (12.8 m s) (25.6 m s) (3.28 ms) (6.55 ms) (12.8 m s) (25.6 m s) 2 7 1/f x 2 8 1/f x 2 15 1/f x 2 16 1/f x 2 7 1/f x 2 8 1/f x (25.6 m s) (51.2 m s) (6.55 ms) (13.1 ms) (25.6 m s) (51.2 m s) 2 8 1/f x 2 9 1/f x 2 16 1/f x 2 17 1/f x 2 8 1/f x 2 9 1/f x (51.2 m s) (102.4 m s) (13.1 ms) (26.2 ms) (51.2 m s) (102.4 m s) 2 9 1/f x 2 10 1/f x 2 17 1/f x 2 18 1/f x 2 9 1/f x 2 10 1/f x (102.4 m s) (204.8 m s) (26.2 ms) (52.4 ms) (102.4 m s) (204.8 m s) 2 11 1/f x 2 12 1/f x 2 19 1/f x 2 20 1/f x 2 11 1/f x 2 12 1/f x (409.6 m s) (819.2 m s) (104.9 ms) (209.7 ms) (409.6 m s) (819.2 m s) remarks 1. f x : main system clock oscillation frequency 2. mcs : oscillation mode selection register bit 0 3. values in parentheses when operated at f x = 5.0 mhz.
171 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 (2) external event counter the number of pulses of an externally input signal can be measured. (3) square-wave output a square wave with any selected frequency can be output. table 9-2. 8-bit timer/event counters 1 and 2 square-wave output ranges minimum pulse width maximum pulse width resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 1/f x 2 2 1/f x 2 9 1/f x 2 10 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (102.4 m s) (204.8 m s) (400 ns) (800 ns) 2 2 1/f x 2 3 1/f x 2 10 1/f x 2 11 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 m s) (204.8 m s) (409.6 m s) (800 ns) (1.6 m s) 2 3 1/f x 2 4 1/f x 2 11 1/f x 2 12 1/f x 2 3 1/f x 2 4 1/f x (1.6 m s) (3.2 m s) (409.6 m s) (819.2 m s) (1.6 m s) (3.2 m s) 2 4 1/f x 2 5 1/f x 2 12 1/f x 2 13 1/f x 2 4 1/f x 2 5 1/f x (3.2 m s) (6.4 m s) (819.2 m s) (1.64 ms) (3.2 m s) (6.4 m s) 2 5 1/f x 2 6 1/f x 2 13 1/f x 2 14 1/f x 2 5 1/f x 2 6 1/f x (6.4 m s) (12.8 m s) (1.64 ms) (3.28 ms) (6.4 m s) (12.8 m s) 2 6 1/f x 2 7 1/f x 2 14 1/f x 2 15 1/f x 2 6 1/f x 2 7 1/f x (12.8 m s) (25.6 m s) (3.28 ms) (6.55 ms) (12.8 m s) (25.6 m s) 2 7 1/f x 2 8 1/f x 2 15 1/f x 2 16 1/f x 2 7 1/f x 2 8 1/f x (25.6 m s) (51.2 m s) (6.55 ms) (13.1 ms) (25.6 m s) (51.2 m s) 2 8 1/f x 2 9 1/f x 2 16 1/f x 2 17 1/f x 2 8 1/f x 2 9 1/f x (51.2 m s) (102.4 m s) (13.1 ms) (26.2 ms) (51.2 m s) (102.4 m s) 2 9 1/f x 2 10 1/f x 2 17 1/f x 2 18 1/f x 2 9 1/f x 2 10 1/f x (102.4 m s) (204.8 m s) (26.2 ms) (52.4 ms) (102.4 m s) (204.8 m s) 2 11 1/f x 2 12 1/f x 2 19 1/f x 2 20 1/f x 2 11 1/f x 2 12 1/f x (409.6 m s) (819.2 m s) (104.9 ms) (209.7 ms) (409.6 m s) (819.2 m s) remarks 1. f x : main system clock oscillation frequency 2. mcs : oscillation mode selection register bit 0 3. values in parentheses when operated at f x = 5.0 mhz.
172 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer interrupts can be generated at the preset time intervals. table 9-3. interval times when 8-bit timer/event counters 1 and 2 are used as 16-bit timer/event counters minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 1/f x 2 2 1/f x 2 17 1/f x 2 18 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 2 1/f x 2 3 1/f x 2 18 1/f x 2 19 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 m s) (52.4 ms) (104.9 ms) (800 ns) (1.6 m s) 2 3 1/f x 2 4 1/f x 2 19 1/f x 2 20 1/f x 2 3 1/f x 2 4 1/f x (1.6 m s) (3.2 m s) (104.9 ms) (209.7 ms) (1.6 m s) (3.2 m s) 2 4 1/f x 2 5 1/f x 2 20 1/f x 2 21 1/f x 2 4 1/f x 2 5 1/f x (3.2 m s) (6.4 m s) (209.7 ms) (419.4 ms) (3.2 m s) (6.4 m s) 2 5 1/f x 2 6 1/f x 2 21 1/f x 2 22 1/f x 2 5 1/f x 2 6 1/f x (6.4 m s) (12.8 m s) (419.4 ms) (838.9 ms) (6.4 m s) (12.8 m s) 2 6 1/f x 2 7 1/f x 2 22 1/f x 2 23 1/f x 2 6 1/f x 2 7 1/f x (12.8 m s) (25.6 m s) (838.9 ms) (1.7 s) (12.8 m s) (25.6 m s) 2 7 1/f x 2 8 1/f x 2 23 1/f x 2 24 1/f x 2 7 1/f x 2 8 1/f x (25.6 m s) (51.2 m s) (1.7 s) (3.4 s) (25.6 m s) (51.2 m s) 2 8 1/f x 2 9 1/f x 2 24 1/f x 2 25 1/f x 2 8 1/f x 2 9 1/f x (51.2 m s) (102.4 m s) (3.4 s) (6.7 s) (51.2 m s) (102.4 m s) 2 9 1/f x 2 10 1/f x 2 25 1/f x 2 26 1/f x 2 9 1/f x 2 10 1/f x (102.4 m s) (204.8 m s) (6.7 s) (13.4 s) (102.4 m s) (204.8 m s) 2 11 1/f x 2 12 1/f x 2 27 1/f x 2 28 1/f x 2 11 1/f x 2 12 1/f x (409.6 m s) (819.2 m s) (26.8 s) (53.7 s) (409.6 m s) (819.2 m s) remarks 1. f x : main system clock oscillation frequency 2. mcs : oscillation mode selection register bit 0 3. values in parentheses when operated at f x = 5.0 mhz.
173 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 (2) external event counter the number of pulses of an externally input signal can be measured. (3) square-wave output a square wave with any selected frequency can be output. table 9-4. square-wave output ranges when 8-bit timer/event counters 1 and 2 are used as 16-bit timer/event counters minimum pulse width maximum pulse width resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 1/f x 2 2 1/f x 2 17 1/f x 2 18 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 2 1/f x 2 3 1/f x 2 18 1/f x 2 19 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 m s) (52.4 ms) (104.9 ms) (800 ns) (1.6 m s) 2 3 1/f x 2 4 1/f x 2 19 1/f x 2 20 1/f x 2 3 1/f x 2 4 1/f x (1.6 m s) (3.2 m s) (104.9 ms) (209.7 ms) (1.6 m s) (3.2 m s) 2 4 1/f x 2 5 1/f x 2 20 1/f x 2 21 1/f x 2 4 1/f x 2 5 1/f x (3.2 m s) (6.4 m s) (209.7 ms) (419.4 ms) (3.2 m s) (6.4 m s) 2 5 1/f x 2 6 1/f x 2 21 1/f x 2 22 1/f x 2 5 1/f x 2 6 1/f x (6.4 m s) (12.8 m s) (419.4 ms) (838.9 ms) (6.4 m s) (12.8 m s) 2 6 1/f x 2 7 1/f x 2 22 1/f x 2 23 1/f x 2 6 1/f x 2 7 1/f x (12.8 m s) (25.6 m s) (838.9 ms) (1.7 s) (12.8 m s) (25.6 m s) 2 7 1/f x 2 8 1/f x 2 23 1/f x 2 24 1/f x 2 7 1/f x 2 8 1/f x (25.6 m s) (51.2 m s) (1.7 s) (3.4 s) (25.6 m s) (51.2 m s) 2 8 1/f x 2 9 1/f x 2 24 1/f x 2 25 1/f x 2 8 1/f x 2 9 1/f x (51.2 m s) (102.4 m s) (3.4 s) (6.7 s) (51.2 m s) (102.4 m s) 2 9 1/f x 2 10 1/f x 2 25 1/f x 2 26 1/f x 2 9 1/f x 2 10 1/f x (102.4 m s) (204.8 m s) (6.7 s) (13.4 s) (102.4 m s) (204.8 m s) 2 11 1/f x 2 12 1/f x 2 27 1/f x 2 28 1/f x 2 11 1/f x 2 12 1/f x (409.6 m s) (819.2 m s) (26.8 s) (53.7 s) (409.6 m s) (819.2 m s) remarks 1. f x : main system clock oscillation frequency 2. mcs : oscillation mode selection register bit 0 3. values in parentheses when operated at f x = 5.0 mhz.
174 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 9.2 8-bit timer/event counters 1 and 2 configurations the 8-bit timer/event counters 1 and 2 consist of the following hardware. table 9-5. 8-bit timer/event counters 1 and 2 configurations item configuration timer register 8 bits 2 (tm1, tm2) register compare register: 8 bits 2 (cr10, cr20) timer output 2 (to1, to2) timer clock select register 1 (tcl1) 8-bit timer mode control register 1 (tmc1) 8-bit timer output control register (toc1) port mode register 3 (pm3) control register
175 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 figure 9-1. 8-bit timer/event counters 1 and 2 block diagram note refer to figures 9-2 and 9-3 for details of 8-bit timer/event counter output control circuits 1 and 2, respectively. selector clear selector selector f xx /2-f xx /2 9 f xx /2 11 ti1/p33 f xx /2-f xx /2 9 f xx /2 11 ti2/p34 4 tmc 12 tce2 tce1 internal bus 8-bit timer/ event counter output control circuit 2 note inttm1 to2/p32 inttm2 to1/p31 4 tcl 17 tcl 16 tcl 15 tcl 14 tcl 13 tcl 12 tcl 11 tcl 10 timer clock select register 1 selector selector 8-bit compare register 10 (cr10) match 8-bit timer register 1 (tm1) 4 8-bit timer register 2 (tm2) match 8-bit compare register 20 (cr20) clear lvs2 lvr2 toc 15 toe2 lvs1 lvr1 toc 11 toe1 8-bit timer output control register internal bus 8-bit timer mode control register 8-bit timer/ event counter output control circuit 1 note 4
176 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 figure 9-2. block diagram of 8-bit timer/event counter output control circuit 1 remark the section in the broken line is an output control circuit. figure 9-3. block diagram of 8-bit timer/event counter output control circuit 2 remarks 1. the section in the broken line is an output control circuit. 2. f sck : serial clock frequency lvr1 lvs1 toc11 inttm1 r s inv q p31 output latch toe1 pm31 to1/p31 level f/f (lv1) lvr2 lvs2 toc15 inttm2 r s inv level f/f (lv2) f sck p32 output latch pm32 toe2 to2/p32 q
177 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 (1) compare registers 10 and 20 (cr10, cr20) these are 8-bit registers to compare the value set to cr10 to the 8-bit timer register 1 (tm1) count value, and the value set to cr20 to the 8-bit timer register 2 (tm2) count value, and, if they match, generate an interrupt request (inttm1 and inttm2, respectively). cr10 and cr20 are set with an 8-bit memory manipulation instruction. they cannot be set with a 16-bit memory manipulation instruction. when the compare register is used as 8-bit timer/event counter, the 00h to ffh values can be set. when the compare register is used as 16-bit timer/event counter, the 0000h to ffffh values can be set. reset input makes cr10 and cr20 undefined. caution when using the compare register as 16-bit timer/event counter, be sure to set data after stopping timer operation. (2) 8-bit timer registers 1, 2 (tm1, tm2) these are 8-bit registers to count count pulses. when tm1 and tm2 are used in the 8-bit timer 2-channel mode, they are read with an 8-bit memory manip- ulation instruction. when tm1 and tm2 are used as 16-bit timer 1-channel mode, 16-bit timer (tms) is read with a 16-bit memory manipulation instruction. reset input sets tm1 and tm2 to 00h.
178 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 9.3 8-bit timer/event counters 1 and 2 control registers the following four types of registers are used to control the 8-bit timer/event counter. ? timer clock select register 1 (tcl1) ? 8-bit timer mode control register 1 (tmc1) ? 8-bit timer output control register (toc1) ? port mode register 3 (pm3) (1) timer clock select register 1 (tcl1) this register sets count clocks of 8-bit timer registers 1 and 2. tcl1 is set with an 8-bit memory manipulation instruction. reset input sets tcl1 to 00h.
179 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 figure 9-4. timer clock select register 1 format caution when rewriting tcl1 to other data, stop the timer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. ti1 : 8-bit timer register 1 input pin 4. ti2 : 8-bit timer register 2 input pin 5. mcs : oscillation mode selection register bit 0 6. figures in parentheses apply to operation with f x = 5.0 mhz tcl17 tcl16 tcl15 tcl14 tcl13 tcl12 tcl11 tcl10 76543210 symbol tcl1 ff41h 00h r/w address after reset r/w tcl13 tcl12 tcl11 tcl10 0 0 0 0 ti1 falling edge 0 0 0 1 ti1 rising edge 0110 0111 f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 1000 f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 1001 f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 1010 f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 1011 f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 1100 f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 1101 f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 1110 f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 1111 f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) mcs=1 8-bit timer register 1 count clock selection mcs=0 other than above setting prohibited f xx /2 11 f x /2 11 (2.4 khz) f x /2 12 (1.2 khz) tcl17 tcl16 tcl15 tcl14 0 0 0 0 ti2 falling edge 0 0 0 1 ti2 rising edge 0110 0111 f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 1000 f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 1001 f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 1010 f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 1011 f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 1100 f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 1101 f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 1110 f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 1111 f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) mcs=1 8-bit timer register 2 count clock selection mcs=0 other than above setting prohibited f xx /2 11 f x /2 11 (2.4 khz) f x /2 12 (1.2 khz)
180 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 (2) 8-bit timer mode control register (tmc1) this register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer register 2. tmc1 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc1 to 00h. figure 9-5. 8-bit timer mode control register format cautions 1. switch the operating mode after stopping timer operation. 2. when used as 16-bit timer register, tce1 should be used for operation enable/stop. 0 1 2 3 4 5 6 7 symbol tce1 ff49h 00h r/w address after reset r/w tce2 tmc12 0 0 0 0 0 tmc1 tce1 8-bit timer register 1 operation control 0 operation stop (tm1 clear to 0) 1 operation enable tce2 8-bit timer register 2 operation control operation stop (tm2 clear to 0) operation enable 0 1 tmc12 operating mode selection 8-bit timer register 2 channel mode (tm1, tm2) 16-bit timer register 1 channel mode (tms) 0 1
181 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 (3) 8-bit timer output control register (toc1) this register controls operation of 8-bit timer/event counter output control circuits 1 and 2. it sets/resets the r-s flip-flops (lv1 and lv2) and enables/disables inversion and 8-bit timer output of 8-bit timer registers 1 and 2. toc1 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets toc1 to 00h. figure 9-6. 8-bit timer output control register format cautions 1. be sure to set toc1 after stopping timer operation. 2. after data setting, 0 can be read from lvs1, lvs2, lvr1 and lvr2. 0 1 2 3 4 5 6 7 symbol toe1 toc11 lvr1 lvs1 toe2 toc15 lvr2 lvs2 toc1 ff4fh 00h r/w address after reset r/w toe1 8-bit timer/event counter 1 outptut control 0 output disable (port mode) 1 output enable toc11 8-bit timer/event counter 1 timer output f/f control 0 inverted operation disable 1 inverted operation enable lvs1 lvr1 8-bit timer/event counter 1 timer output f/f status set 0 0 unchanged 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toe2 8-bit timer/event counter 2 output control 0 output disable (port mode) 1 output enable toc15 8-bit timer/event counter 2 timer output f/f control 0 inverted operation disable 1 inverted operation enable lvs2 lvr2 8-bit timer/event counter 2 timer output f/f status set 0 0 unchanged 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited
182 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 (4) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p31/to1 and p32/to2 pins for timer output, set pm31, pm32, and output latches of p31 and p32 to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 9-7. port mode register 3 format 0 1 2 3 4 5 6 7 symbol pm30 ff23h ffh r/w address after reset r/w pm31 pm32 pm33 pm34 pm35 pm36 pm37 pm3 pm3n p3n pin input/output mode selection (n=0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off)
183 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 9.4 8-bit timer/event counters 1 and 2 operations 9.4.1 8-bit timer/event counter mode (1) interval timer operations the 8-bit timer/event counters 1 and 2 operate as interval timers which generate interrupts repeatedly at intervals of the count value preset to 8-bit compare registers 10 and 20 (cr10 and cr20). when the count values of the 8-bit timer registers 1 and 2 (tm1 and tm2) match the values set to cr10 and cr20, counting continues with the tm1 and tm2 values cleared to 0 and the interrupt request signals (inttm1 and inttm2) are generated. count clock of the 8-bit timer register 1 (tm1) can be selected with bits 0 to 3 (tcl10 to tcl13) of the timer clock select register 1 (tcl1). count clock of the 8-bit timer register 2 (tm2) can be selected with bits 4 to 7 (tcl14 to tcl17) of the timer clock select register 1 (tcl1). figure 9-8. interval timer operation timings remark interval time = (n + 1) t : n = 00h to ffh count clock tm1 count value inttm1 cr10 to1 interval time interval time interval time interrupt acknowledge interrupt acknowledge n n n n count start clear clear t 00 01 n 00 01 n 00 01 n
184 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 table 9-6. 8-bit timer/event counter 1 interval time minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 0000 ti1 input cycle 2 8 ti1 input cycle ti1 input edge cycle 0001 ti1 input cycle 2 8 ti1 input cycle ti1 input edge cycle 2 1/f x 2 2 1/f x 2 9 1/f x 2 10 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (102.4 m s) (204.8 m s) (400 ns) (800 ns) 2 2 1/f x 2 3 1/f x 2 10 1/f x 2 11 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 m s) (204.8 m s) (409.6 m s) (800 ns) (1.6 m s) 2 3 1/f x 2 4 1/f x 2 11 1/f x 2 12 1/f x 2 3 1/f x 2 4 1/f x (1.6 m s) (3.2 m s) (409.6 m s) (819.2 m s) (1.6 m s) (3.2 m s) 2 4 1/f x 2 5 1/f x 2 12 1/f x 2 13 1/f x 2 4 1/f x 2 5 1/f x (3.2 m s) (6.4 m s) (819.2 m s) (1.64 ms) (3.2 m s) (6.4 m s) 2 5 1/f x 2 6 1/f x 2 13 1/f x 2 14 1/f x 2 5 1/f x 2 6 1/f x (6.4 m s) (12.8 m s) (1.64 ms) (3.28 ms) (6.4 m s) (12.8 m s) 2 6 1/f x 2 7 1/f x 2 14 1/f x 2 15 1/f x 2 6 1/f x 2 7 1/f x (12.8 m s) (25.6 m s) (3.28 ms) (6.55 ms) (12.8 m s) (25.6 m s) 2 7 1/f x 2 8 1/f x 2 15 1/f x 2 16 1/f x 2 7 1/f x 2 8 1/f x (25.6 m s) (51.2 m s) (6.55 ms) (13.1 ms) (25.6 m s) (51.2 m s) 2 8 1/f x 2 9 1/f x 2 16 1/f x 2 17 1/f x 2 8 1/f x 2 9 1/f x (51.2 m s) (102.4 m s) (13.1 ms) (26.2 ms) (51.2 m s) (102.4 m s) 2 9 1/f x 2 10 1/f x 2 17 1/f x 2 18 1/f x 2 9 1/f x 2 10 1/f x (102.4 m s) (204.8 m s) (26.2 ms) (52.4 ms) (102.4 m s) (204.8 m s) 2 11 1/f x 2 12 1/f x 2 19 1/f x 2 20 1/f x 2 11 1/f x 2 12 1/f x (409.6 m s) (819.2 m s) (104.9 ms) (209.7 ms) (409.6 m s) (819.2 m s) other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. mcs : oscillation mode selection register bit 0 3. values in parentheses when operated at f x = 5.0 mhz. 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 tcl13 tcl12 tcl11 tcl10
185 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 table 9-7. 8-bit timer/event counter 2 interval time minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 0000 ti2 input cycle 2 8 ti2 input cycle ti2 input edge cycle 0001 ti2 input cycle 2 8 ti2 input cycle ti2 input edge cycle 2 1/f x 2 2 1/f x 2 9 1/f x 2 10 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (102.4 m s) (204.8 m s) (400 ns) (800 ns) 2 2 1/f x 2 3 1/f x 2 10 1/f x 2 11 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 m s) (204.8 m s) (409.6 m s) (800 ns) (1.6 m s) 2 3 1/f x 2 4 1/f x 2 11 1/f x 2 12 1/f x 2 3 1/f x 2 4 1/f x (1.6 m s) (3.2 m s) (409.6 m s) (819.2 m s) (1.6 m s) (3.2 m s) 2 4 1/f x 2 5 1/f x 2 12 1/f x 2 13 1/f x 2 4 1/f x 2 5 1/f x (3.2 m s) (6.4 m s) (819.2 m s) (1.64 ms) (3.2 m s) (6.4 m s) 2 5 1/f x 2 6 1/f x 2 13 1/f x 2 14 1/f x 2 5 1/f x 2 6 1/f x (6.4 m s) (12.8 m s) (1.64 ms) (3.28 ms) (6.4 m s) (12.8 m s) 2 6 1/f x 2 7 1/f x 2 14 1/f x 2 15 1/f x 2 6 1/f x 2 7 1/f x (12.8 m s) (25.6 m s) (3.28 ms) (6.55 ms) (12.8 m s) (25.6 m s) 2 7 1/f x 2 8 1/f x 2 15 1/f x 2 16 1/f x 2 7 1/f x 2 8 1/f x (25.6 m s) (51.2 m s) (6.55 ms) (13.1 ms) (25.6 m s) (51.2 m s) 2 8 1/f x 2 9 1/f x 2 16 1/f x 2 17 1/f x 2 8 1/f x 2 9 1/f x (51.2 m s) (102.4 m s) (13.1 ms) (26.2 ms) (51.2 m s) (102.4 m s) 2 9 1/f x 2 10 1/f x 2 17 1/f x 2 18 1/f x 2 9 1/f x 2 10 1/f x (102.4 m s) (204.8 m s) (26.2 ms) (52.4 ms) (102.4 m s) (204.8 m s) 2 11 1/f x 2 12 1/f x 2 19 1/f x 2 20 1/f x 2 11 1/f x 2 12 1/f x (409.6 m s) (819.2 m s) (104.9 ms) (209.7 ms) (409.6 m s) (819.2 m s) other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. mcs : oscillation mode selection register bit 0 3. values in parentheses when operated at f x = 5.0 mhz 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 tcl17 tcl16 tcl15 tcl14
186 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 (2) external event counter operation the external event counter counts the number of external clock pulses to be input to the ti1/p33 and ti2/ p34 pins with 8-bit timer registers 1 and 2 (tm1 and tm2). tm1 and tm2 are incremented each time the valid edge specified with the timer clock select register (tcl1) is input. either the rising or falling edge can be selected. when the tm1 and tm2 counted values match the values of 8-bit compare registers (cr10 and cr20), tm1 and tm2 are cleared to 0 and the interrupt request signals (inttm1 and inttm2) are generated. figure 9-9. external event counter operation timings (with rising edge specified) remark n = 00h to ffh ti1 pin input tm1 count value inttm1 cr10 00 01 02 03 04 05 n-1 n 00 01 02 03 n
187 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 (3) square-wave output a square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers 10 and 20 (cr10 and cr20). the to1/p31 or to2/p32 pin output status is reversed at intervals of the count value preset to cr10 or cr20 by setting bit 0 (toe1) or bit 4 (toe2) of the 8-bit timer output control register (toc1) to 1. this enables a square wave with any selected frequency to be output. table 9-8. 8-bit timer/event counters 1 and 2 square-wave output ranges minimum pulse width maximum pulse width resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 1/f x 2 2 1/f x 2 9 1/f x 2 10 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (102.4 m s) (204.8 m s) (400 ns) (800 ns) 2 2 1/f x 2 3 1/f x 2 10 1/f x 2 11 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 m s) (204.8 m s) (409.6 m s) (800 ns) (1.6 m s) 2 3 1/f x 2 4 1/f x 2 11 1/f x 2 12 1/f x 2 3 1/f x 2 4 1/f x (1.6 m s) (3.2 m s) (409.6 m s) (819.2 m s) (1.6 m s) (3.2 m s) 2 4 1/f x 2 5 1/f x 2 12 1/f x 2 13 1/f x 2 4 1/f x 2 5 1/f x (3.2 m s) (6.4 m s) (819.2 m s) (1.64 ms) (3.2 m s) (6.4 m s) 2 5 1/f x 2 6 1/f x 2 13 1/f x 2 14 1/f x 2 5 1/f x 2 6 1/f x (6.4 m s) (12.8 m s) (1.64 ms) (3.28 ms) (6.4 m s) (12.8 m s) 2 6 1/f x 2 7 1/f x 2 14 1/f x 2 15 1/f x 2 6 1/f x 2 7 1/f x (12.8 m s) (25.6 m s) (3.28 ms) (6.55 ms) (12.8 m s) (25.6 m s) 2 7 1/f x 2 8 1/f x 2 15 1/f x 2 16 1/f x 2 7 1/f x 2 8 1/f x (25.6 m s) (51.2 m s) (6.55 ms) (13.1 ms) (25.6 m s) (51.2 m s) 2 8 1/f x 2 9 1/f x 2 16 1/f x 2 17 1/f x 2 8 1/f x 2 9 1/f x (51.2 m s) (102.4 m s) (13.1 ms) (26.2 ms) (51.2 m s) (102.4 m s) 2 9 1/f x 2 10 1/f x 2 17 1/f x 2 18 1/f x 2 9 1/f x 2 10 1/f x (102.4 m s) (204.8 m s) (26.2 ms) (52.4 ms) (102.4 m s) (204.8 m s) 2 11 1/f x 2 12 1/f x 2 19 1/f x 2 20 1/f x 2 11 1/f x 2 12 1/f x (409.6 m s) (819.2 m s) (104.9 ms) (209.7 ms) (409.6 m s) (819.2 m s) remarks 1. f x : main system clock oscillation frequency 2. mcs : oscillation mode selection register bit 0 3. values in parentheses when operated at f x = 5.0 mhz.
188 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 9.4.2 16-bit timer/event counter mode when bit 2 (tmc12) of 8-bit timer mode control register 1 (tmc1) is set to 1 and the 16-bit timer/counter mode is selected, the overflow signal of 8-bit timer/event counter 1 (tm1) becomes a count clock of 8-bit timer/event counter 2 (tm2). when a 2-channel 8-bit timer/event counter is used in the 16-bit timer/event counter mode, the count clock is selected with bits 0 to 3 (tcl10 to tcl13) of tcl1. count operation enable/disable is selected with bit 0 (tce1) of tmc1. (1) interval timer the 8-bit timer/event counter operates as interval timer which generates interrupts repeatedly at intervals of the count value preset to 2-channel 8-bit compare registers 10 and 20 (cr10 and cr20). when the 8-bit timer register 1 (tm1) and cr10 values match and the 8-bit timer register 2 (tm2) and cr20 values match, counting continues with the tm1 and tm2 values cleared to 0 and the interrupt request signal (inttm2) is generated. count clock can be selected with bits 0 to 3 (tcl10 to tcl13) of the timer clock select register 1 (tcl1). figure 9-10. interval timer operation timing remark interval time = (n + 1) t : n = 0000h to ffffh caution even if the 16-bit timer/event counter mode is used, when the tm1 count value matches the cr10 value, interrupt request (inttm1) is generated and the f/f of 8-bit timer/event counter output control circuit 1 is inverted. thus, when using 8-bit timer/event counter as 16-bit interval timer, set the inttm1 mask flag tmmk1 to 1 to disable inttm1 acknowledg- ment. when reading the 16-bit timer (tms) count value, use the 16-bit memory manipulation instruction. count clock tms (tm1, tm2) count value cr10, cr20 inttm2 to2 interval time interval time interval time interrupt acknowledge interrupt acknowledge nn nn count start clear clear 0000 0001 n 0000 0001 n 0000 0001 n t
189 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 table 9-9. interval times when 2-channel 8-bit timer/event counters (tm1 and tm2) are used as 16-bit timer/event counter minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 0000 ti1 input cycle 2 8 ti1 input cycle ti1 input edge cycle 0001 ti1 input cycle 2 8 ti1 input cycle ti1 input edge cycle 2 1/f x 2 2 1/f x 2 17 1/f x 2 18 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 2 1/f x 2 3 1/f x 2 18 1/f x 2 19 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 m s) (52.4 ms) (104.9 ms) (800 ns) (1.6 m s) 2 3 1/f x 2 4 1/f x 2 19 1/f x 2 20 1/f x 2 3 1/f x 2 4 1/f x (1.6 m s) (3.2 m s) (104.9 ms) (209.7 ms) (1.6 m s) (3.2 m s) 2 4 1/f x 2 5 1/f x 2 20 1/f x 2 21 1/f x 2 4 1/f x 2 5 1/f x (3.2 m s) (6.4 m s) (209.7 ms) (419.4 ms) (3.2 m s) (6.4 m s) 2 5 1/f x 2 6 1/f x 2 21 1/f x 2 22 1/f x 2 5 1/f x 2 6 1/f x (6.4 m s) (12.8 m s) (419.4 ms) (838.9 ms) (6.4 m s) (12.8 m s) 2 6 1/f x 2 7 1/f x 2 22 1/f x 2 23 1/f x 2 6 1/f x 2 7 1/f x (12.8 m s) (25.6 m s) (838.9 ms) (1.7 s) (12.8 m s) (25.6 m s) 2 7 1/f x 2 8 1/f x 2 23 1/f x 2 24 1/f x 2 7 1/f x 2 8 1/f x (25.6 m s) (51.2 m s) (1.7 s) (3.4 s) (25.6 m s) (51.2 m s) 2 8 1/f x 2 9 1/f x 2 24 1/f x 2 25 1/f x 2 8 1/f x 2 9 1/f x (51.2 m s) (102.4 m s) (3.4 s) (6.7 s) (51.2 m s) (102.4 m s) 2 9 1/f x 2 10 1/f x 2 25 1/f x 2 26 1/f x 2 9 1/f x 2 10 1/f x (102.4 m s) (204.8 m s) (6.7 s) (13.4 s) (102.4 m s) (204.8 m s) 2 11 1/f x 2 12 1/f x 2 27 1/f x 2 28 1/f x 2 11 1/f x 2 12 1/f x (409.6 m s) (819.2 m s) (26.8 s) (53.7 s) (409.6 m s) (819.2 m s) other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. mcs : oscillation mode selection register bit 0 3. values in parentheses when operated at f x = 5.0 mhz. 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 tcl13 tcl12 tcl11 tcl10
190 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 (2) external event counter operations the external event counter counts the number of external clock pulses to be input to the ti1/p33 pin with 2-channel 8-bit timer registers 1 and 2 (tm1 and tm2). tm1 and tm2 are incremented each time the valid edge specified with the timer clock select register 1 (tcl1) is input. either the rising or falling edge can be selected. when the tm1 and tm2 counted values match the values of 8-bit compare registers 10 and 20 (cr10 and cr20), tm1 and tm2 are cleared to 0 and the interrupt request signal (inttm2) is generated. figure 9-11. external event counter operation timings (with rising edge specified) caution even if the 16-bit timer/event counter mode is used, when the tm1 count value matches the cr10 value, interrupt request (inttm1) is generated and the f/f of 8-bit timer/event counter output control circuit 1 is inverted. thus, when using 8-bit timer/event counter as 16-bit interval timer, set the inttm1 mask flag tmmk1 to 1 to disable inttm1 acknowledg- ment. when reading the 16-bit timer (tms) count value, use the 16-bit memory manipulation instruction. ti1 pin input tm1, tm2 count value cr10, cr20 inttm2 0000 0001 0002 0003 0004 0005 n-1 n 0000 0001 0002 0003 n
191 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 (3) square-wave output operation a square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers 10 and 20 (cr10 and cr20). the to2/p32 pin output status is reversed at intervals of the count value preset to cr10 and cr20 by setting bit 4 (toe2) of the 8-bit timer output control register (toc1) to 1. this enables a square wave with any selected frequency to be output. table 9-10. square-wave output ranges when 2-channel 8-bit timer/event counters (tm1 and tm2) are used as 16-bit timer/event counter minimum pulse width maximum pulse width resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 1/f x 2 2 1/f x 2 17 1/f x 2 18 1/f x 2 1/f x 2 2 1/f x (400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 2 1/f x 2 3 1/f x 2 18 1/f x 2 19 1/f x 2 2 1/f x 2 3 1/f x (800 ns) (1.6 m s) (52.4 ms) (104.9 ms) (800 ns) (1.6 m s) 2 3 1/f x 2 4 1/f x 2 19 1/f x 2 20 1/f x 2 3 1/f x 2 4 1/f x (1.6 m s) (3.2 m s) (104.9 ms) (209.7 ms) (1.6 m s) (3.2 m s) 2 4 1/f x 2 5 1/f x 2 20 1/f x 2 21 1/f x 2 4 1/f x 2 5 1/f x (3.2 m s) (6.4 m s) (209.7 ms) (419.4 ms) (3.2 m s) (6.4 m s) 2 5 1/f x 2 6 1/f x 2 21 1/f x 2 22 1/f x 2 5 1/f x 2 6 1/f x (6.4 m s) (12.8 m s) (419.4 ms) (838.9 ms) (6.4 m s) (12.8 m s) 2 6 1/f x 2 7 1/f x 2 22 1/f x 2 23 1/f x 2 6 1/f x 2 7 1/f x (12.8 m s) (25.6 m s) (838.9 ms) (1.7 s) (12.8 m s) (25.6 m s) 2 7 1/f x 2 8 1/f x 2 23 1/f x 2 24 1/f x 2 7 1/f x 2 8 1/f x (25.6 m s) (51.2 m s) (1.7 s) (3.4 s) (25.6 m s) (51.2 m s) 2 8 1/f x 2 9 1/f x 2 24 1/f x 2 25 1/f x 2 8 1/f x 2 9 1/f x (51.2 m s) (102.4 m s) (3.4 s) (6.7 s) (51.2 m s) (102.4 m s) 2 9 1/f x 2 10 1/f x 2 25 1/f x 2 26 1/f x 2 9 1/f x 2 10 1/f x (102.4 m s) (204.8 m s) (6.7 s) (13.4 s) (102.4 m s) (204.8 m s) 2 11 1/f x 2 12 1/f x 2 27 1/f x 2 28 1/f x 2 11 1/f x 2 12 1/f x (409.6 m s) (819.2 m s) (26.8 s) (53.7 s) (409.6 m s) (819.2 m s) remarks 1. f x : main system clock oscillation frequency 2. mcs : oscillation mode selection register bit 0 3. values in parentheses when operated at f x = 5.0 mhz.
192 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 9.5 cautions on 8-bit timer/event counters 1 and 2 (1) timer start errors an error with a maximum of one clock may occur concerning the time required for a match signal to be gener- ated after timer start. this is because 8-bit timer registers 1 and 2 (tm1 and tm2) are started asynchronously with the count pulse. figure 9-12. 8-bit timer registers 1 and 2 start timing (2) 8-bit compare register 10 and 20 setting the 8-bit compare registers 10 and 20 (cr10 and cr20) can be set to 00h. thus, when these 8-bit compare registers are used as event counters, one-pulse count operation can be carried out. when the 8-bit compare register is used as 16-bit timer/event counter, write data to cr10 and cr20 after setting bit 0 (tce1) of the 8-bit timer mode control register 1 to 0 and stopping timer operation. figure 9-13. external event counter operation timing count pulse tm1, tm2 count value 00h 01h 02h 03h 04h timer start ti1, ti2, input cr10, cr20 tm1, tm2 count value to1, to2 interrupt request flag 00h 00h 00h 00h 00h
193 chapter 9 8-bit timer/event counters 1 and 2 users manual u10105ej4v1um00 (3) operation after compare register change during timer count operation if the values after the 8-bit compare registers 10 and 20 (cr10 and cr20) are changed are smaller than those of 8-bit timer registers 1 and 2 (tm1 and tm2), tm1 and tm2 continue counting, overflow and then restart counting from 0. thus, if the value (m) after cr10 and cr20 change is smaller than value (n) before the change, it is necessary to restart the timer after changing cr10 and cr20. figure 9-14. timing after compare register change during timer count operation remark n > x > m count pulse cr10, cr20 tm1, tm2 count value x-1 x ffffh 0000h 0001h 0002h m n
194 users manual u10105ej4v1um00 [memo]
195 users manual u10105ej4v1um00 chapter 10 watch timer 10.1 watch timer functions the watch timer has the following functions. ? watch timer ? interval timer the watch timer and the interval timer can be used simultaneously. (1) watch timer when the 32.768 khz subsystem clock is used, a flag (wtif) is set at 0.5 second or 0.25 second intervals. when the 4.19 mhz (standard: 4.194304 mhz) main system clock is used, a flag (wtif) is set at 0.5 second or 0.25 second intervals. caution 0.5-second intervals cannot be generated with the 5.0-mhz main system clock. you should switch to the 32.768 khz subsystem clock to generate 0.5-second intervals. (2) interval timer interrupt requests (inttm3) are generated at the preset time interval. table 10-1. interval timer interval time when operated at when operated at when operated at f xx = 5.0 mhz f xx = 4.19 mhz f xt = 32.768 khz 2 4 1/f w 410 m s 488 m s 488 m s 2 5 1/f w 819 m s 977 m s 977 m s 2 6 1/f w 1.64 ms 1.95 ms 1.95 ms 2 7 1/f w 3.28 ms 3.91 ms 3.91 ms 2 8 1/f w 6.55 ms 7.81 ms 7.81 ms 2 9 1/f w 13.1 ms 15.6 ms 15.6 ms remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency (f xx /2 7 or f xt ) interval time
196 chapter 10 watch timer users manual u10105ej4v1um00 10.2 watch timer configuration the watch timer consists of the following hardware. table 10-2. watch timer configuration item configuration counter 5 bits 1 timer clock select register 2 (tcl2) watch timer mode control register (tmc2) 10.3 watch timer control registers the following two types of registers are used to control the watch timer. ? timer clock select register 2 (tcl2) ? watch timer mode control register (tmc2) (1) timer clock select register 2 (tcl2) this register sets the watch timer count clock. tcl2 is set with an 8-bit memory manipulation instruction. reset input sets tcl2 to 00h. remark besides setting the watch timer count clock, tcl2 sets the watchdog timer count clock and buzzer output frequency. control register
197 chapter 10 watch timer users manual u10105ej4v1um00 figure 10-1. watch timer block diagram * tmc21 prescaler selector intwt 5-bit counter f w 2 14 f w 2 13 inttm3 to 16-bit timer/ event counter watch timer mode control register tmc26 tmc25 tmc24 tmc23 tmc22 tmc21 tmc20 internal bus tcl24 timer clock select register 2 3 f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 f w f xx /2 7 f xt clear clear selector selector selector to lcd controller/driver
198 chapter 10 watch timer users manual u10105ej4v1um00 figure 10-2. timer clock select register 2 format caution when rewriting tcl2 to other data, stop the timer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. : don't care 5. mcs : oscillation mode selection register bit 0 6. figures in parentheses apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. tcl27 7 tcl26 6 tcl25 tcl24 4 0 3210 ff42h address tcl2 symbol tcl22 tcl21 tcl20 5 00h after reset r/w r/w 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 tcl22 tcl21 tcl20 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 f xx /2 9 f xx /2 11 mcs=1 f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) f x /2 11 (2.4 khz) mcs=0 f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) f x /2 12 (1.2 khz) watchdog timer count clock selection 0 1 tcl24 f xx /2 7 f xt (32.768 khz) mcs=1 f x /2 7 (39.1 khz) mcs=0 f x /2 8 (19.5 khz) watch timer count clock selection 0 1 1 1 1 0 0 1 1 0 1 0 1 tcl27 tcl26 tcl25 buzzer output disable f xx /2 9 f xx /2 10 f xx /2 11 setting prohibited mcs=1 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) mcs=0 f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) f x /2 12 (1.2 khz) buzzer output frequency selection
199 chapter 10 watch timer users manual u10105ej4v1um00 (2) watch timer mode control register (tmc2) this register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/ disables prescaler and 5-bit counter operations. tmc2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc2 to 00h. figure 10-3. watch timer mode control register format caution when the watch timer is used, the prescaler should not be cleared frequently. remark f w : watch timer clock frequency (f xx /2 7 or f xt ) f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency 0 7 tmc26 6 tmc25 tmc24 4 tmc23 3210 ff4ah address tmc2 symbol tmc22 tmc21 tmc20 5 00h after reset r/w r/w 0 1 tmc23 f xx =5.0 mhz operation 2 14 /f w (0.4 sec) 2 13 /f w (0.2 sec) watch flag set time selection 0 0 0 0 1 1 other than above 0 0 1 1 0 0 0 1 0 1 0 1 tmc26 tmc25 tmc24 f xx =5.0 mhz operation 2 4 /f w (410 s) 2 5 /f w (819 s) 2 6 /f w (1.64 ms) 2 7 /f w (3.28 ms) 2 8 /f w (6.55 ms) 2 9 /f w (13.1 ms) setting prohibited f xx =4.19 mhz operation 2 4 /f w (488 s) 2 5 /f w (977 s) 2 6 /f w (1.95 ms) 2 7 /f w (3.91 ms) 2 8 /f w (7.81 ms) 2 9 /f w (15.6 ms) f xt =32.768 khz operation 2 4 /f w (488 s) 2 5 /f w (977 s) 2 6 /f w (1.95 ms) 2 7 /f w (3.91 ms) 2 8 /f w (7.81 ms) 2 9 /f w (15.6 ms) prescaler interval time selection m m m m m m f xx =4.19 mhz operation 2 14 /f w (0.5 sec) 2 13 /f w (0.25 sec) f xt =32.768 khz operation 2 14 /f w (0.5 sec) 2 13 /f w (0.25 sec) tmc22 0 1 5-bit counter operation control clear after operation stop operation enable tmc21 0 1 prescaler operation control clear after operation stop operation enable tmc20 0 1 watch operating mode selection normal operating mode (flag set at f w /2 14 ) fast feed operating mode (flag set at f w /2 5 )
200 chapter 10 watch timer users manual u10105ej4v1um00 10.4 watch timer operations 10.4.1 watch timer operation when the 32.768-khz subsystem clock or 4.19-mhz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. the watch timer sets the test input flag (wtif) to 1 at the constant time interval. the standby state (stop mode/ halt mode) can be cleared by setting wtif to 1. when bit 2 (timc22) of the watch timer mode control register is set to 0, the 5-bit counter is cleared and the count operation stops. for simultaneous operation of the interval timer, zero-second start can be achieved by setting tmc22 to 0 (maximum error: 26.2 ms when operated at f xx = 5.0 mhz). 10.4.2 interval timer operation the watch timer operates as interval timer which generates interrupts repeatedly at an interval of the preset count value. the interval time can be selected with bits 4 to 6 (tmc24 to tmc26) of the watch timer mode control register. table 10-3. interval timer interval time when operated at when operated at when operated at f xx = 5.0 mhz f xx = 4.19 mhz f xt = 32.768 khz 000 2 4 1/f w 410 m s 488 m s 488 m s 001 2 5 1/f w 819 m s 977 m s 977 m s 010 2 6 1/f w 1.64 ms 1.95 ms 1.95 ms 011 2 7 1/f w 3.28 ms 3.91 ms 3.91 ms 100 2 8 1/f w 6.55 ms 7.81 ms 7.81 ms 101 2 9 1/f w 13.1 ms 15.6 ms 15.6 ms other than above setting prohibited remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency (f xx /2 7 or f xt ) tmc26 tmc25 tmc24 interval time
201 users manual u10105ej4v1um00 chapter 11 watchdog timer 11.1 watchdog timer functions the watchdog timer has the following functions. ? watchdog timer ? interval timer caution select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (wdtm). (1) watchdog timer mode an inadvertent program loop is detected. upon detection of the inadvertent program loop, a non-maskable interrupt or reset can be generated. table 11-1. watchdog timer inadvertent program overrun detection times runaway detection time mcs = 1 mcs = 0 2 11 1/f xx 2 11 1/f x (410 m s) 2 12 1/f x (819 m s) 2 12 1/f xx 2 12 1/f x (819 m s) 2 13 1/f x (1.64 ms) 2 13 1/f xx 2 13 1/f x (1.64 ms) 2 14 1/f x (3.28 ms) 2 14 1/f xx 2 14 1/f x (3.28 ms) 2 15 1/f x (6.55 ms) 2 15 1/f xx 2 15 1/f x (6.55 ms) 2 16 1/f x (13.1 ms) 2 16 1/f xx 2 16 1/f x (13.1 ms) 2 17 1/f x (26.2 ms) 2 17 1/f xx 2 17 1/f x (26.2 ms) 2 18 1/f x (52.4 ms) 2 19 1/f xx 2 19 1/f x (104.9 ms) 2 20 1/f x (209.7 ms) remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs : oscillation mode selection register bit 0 4. figures in parentheses apply to operation with f x = 5.0 mhz.
202 chapter 11 watchdog timer users manual u10105ej4v1um00 (2) interval timer mode interrupts are generated at the preset time intervals. table 11-2. interval times interval time mcs = 1 cs = 0 2 11 1/f xx 2 11 1/f x (410 m s) 2 12 1/f x (819 m s) 2 12 1/f xx 2 12 1/f x (819 m s) 2 13 1/f x (1.64 ms) 2 13 1/f xx 2 13 1/f x (1.64 ms) 2 14 1/f x (3.28 ms) 2 14 1/f xx 2 14 1/f x (3.28 ms) 2 15 1/f x (6.55 ms) 2 15 1/f xx 2 15 1/f x (6.55 ms) 2 16 1/f x (13.1 ms) 2 16 1/f xx 2 16 1/f x (13.1 ms) 2 17 1/f x (26.2 ms) 2 17 1/f xx 2 17 1/f x (26.2 ms) 2 18 1/f x (52.4 ms) 2 19 1/f xx 2 19 1/f x (104.9 ms) 2 20 1/f x (209.7 ms) remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs : oscillation mode selection register bit 0 4. figures in parentheses apply to operation with f x = 5.0 mhz.
203 chapter 11 watchdog timer users manual u10105ej4v1um00 11.2 watchdog timer configuration the watchdog timer consists of the following hardware. table 11-3. watchdog timer configuration item configuration timer clock select register 2 (tcl2) watchdog timer mode register (wdtm) figure 11-1. watchdog timer block diagram control register prescaler f xx 2 4 f xx 2 5 f xx 2 6 f xx 2 7 f xx 2 8 f xx 2 9 selector watchdog timer mode register internal bus internal bus tcl22 tcl21 tcl20 f xx /2 3 f xx 2 11 timer clock select register 2 3 wdtm4 wdtm3 8-bit counter tmmk4 run tmif4 intwdt maskable interrupt request intwdt non-maskable interrupt request reset control circuit
204 chapter 11 watchdog timer users manual u10105ej4v1um00 11.3 watchdog timer control registers the following two types of registers are used to control the watchdog timer. ? timer clock select register 2 (tcl2) ? watchdog timer mode register (wdtm) (1) timer clock select register 2 (tcl2) this register sets the watchdog timer count clock. tcl2 is set with 8-bit memory manipulation instruction. reset input sets tcl2 to 00h. remark besides setting the watchdog timer count clock, tcl2 sets the watch timer count clock and buzzer output frequency.
205 chapter 11 watchdog timer users manual u10105ej4v1um00 figure 11-2. timer clock select register 2 format caution when rewriting tcl2 to other data, stop the timer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. : don't care 5. mcs : oscillation mode selection register bit 0 6. figures in parentheses apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. tcl27 7 tcl26 6 tcl25 tcl24 4 0 3210 ff42h address tcl2 symbol tcl22 tcl21 tcl20 5 00h after reset r/w r/w 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 tcl22 tcl21 tcl20 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 f xx /2 9 f xx /2 11 mcs=1 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 11 mcs=0 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 10 f x /2 12 watchdog timer count clock selection 0 1 tcl24 f xx /2 7 f xt (32.768 khz) mcs=1 f x /2 7 (39.1 khz) mcs=0 f x /2 8 (19.5 khz) watch timer count clock selection 0 1 1 1 1 0 0 1 1 0 1 0 1 tcl27 tcl26 tcl25 buzzer output disable f xx /2 9 f xx /2 10 f xx /2 11 setting prohibited mcs=1 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) mcs=0 f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) f x /2 12 (1.2 khz) buzzer output frequency selection (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) (9.8 khz) (2.4 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) (9.8 khz) (4.9 khz) (1.2 khz)
206 chapter 11 watchdog timer users manual u10105ej4v1um00 (2) watchdog timer mode register (wdtm) this register sets the watchdog timer operating mode and enables/disables counting. wdtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets wdtm to 00h. figure 11-3. watchdog timer mode register format notes 1. once set to 1, wdtm3 and wdtm4 cannot be cleared to 0 by software. 2. once set to 1, run cannot be cleared to 0 by software. thus, once counting starts, it can only be stopped by reset input. caution when 1 is set in run so that the watchdog timer is cleared, the actual overflow time is up to 0.5 % shorter than the time set by timer clock select register 2. rum 7 0 6 0 wdtm4 4 wdtm3 3210 fff9h address wdtm symbol 000 5 00h after reset r/w r/w run 0 1 watchdog timer operation mode selection note 2 count stop counter is cleared and counting starts. wdtm3 0 1 0 1 watchdog timer operation mode selection note 1 operation stop interval timer mode (maskable interrupt occurs upon generation of an overflow.) watchdog timer mode 1 (non-maskable interrupt occurs upon generation of an overflow.) watchdog timer mode 2 (reset operation is activated upon generation of an overflow.) wdtm4 0 0 1 1
207 chapter 11 watchdog timer users manual u10105ej4v1um00 11.4 watchdog timer operations 11.4.1 watchdog timer operation when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1, the watchdog timer is operated to detect any inadvertent program loop. the watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to 2 (tcl20 to tcl22) of the timer clock select register 2 (tcl2). watchdog timer starts by setting bit 7 (run) of wdtm to 1. after the watchdog timer is started, set run to 1 within the set overrun time interval. the watchdog timer can be cleared and counting is started by setting run to 1. if run is not set to 1 and the inadvertent program loop detection time is past, system reset or a non-maskable interrupt is generated according to the wdtm bit 3 (wdtm3) value. the watchdog timer continues operating in the halt mode but it stops in the stop mode. thus, set run to 1 before the stop mode is set, clear the watchdog timer and then execute the stop instruction. cautions 1. the actual overrun detection time may be shorter than the set time by a maximum of 0.5 %. 2. when the subsystem clock is selected for cpu clock, watchdog timer count operation is stopped. table 11-4. watchdog timer overrun detection time tcl22 tcl21 tcl20 runaway detection time mcs = 1 mcs = 0 000 2 11 1/f xx 2 11 1/f x (410 m s) 2 12 1/f x (819 m s) 001 2 12 1/f xx 2 12 1/f x (819 m s) 2 13 1/f x (1.64 ms) 010 2 13 1/f xx 2 13 1/f x (1.64 ms) 2 14 1/f x (3.28 ms) 011 2 14 1/f xx 2 14 1/f x (3.28 ms) 2 15 1/f x (6.55 ms) 100 2 15 1/f xx 2 15 1/f x (6.55 ms) 2 16 1/f x (13.1 ms) 101 2 16 1/f xx 2 16 1/f x (13.1 ms) 2 17 1/f x (26.2 ms) 110 2 17 1/f xx 2 17 1/f x (26.2 ms) 2 18 1/f x (52.4 ms) 111 2 19 1/f xx 2 19 1/f x (104.9 ms) 2 20 1/f x (209.7 ms) remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs : oscillation mode selection register bit 0 4. figures in parentheses apply to operation with f x = 5.0 mhz.
208 chapter 11 watchdog timer users manual u10105ej4v1um00 11.4.2 interval timer operation the watchdog timer operates as an interval timer which generates interrupts repeatedly at an interval of the preset count value when bit 3 (wdtm3) and bit 4 (wdtm4) of the watchdog timer mode register (wdtm) are set to 1 and 0, respectively. when the watchdog timer operated as interval timer, the interrupt mask flag (tmmk4) and priority specify flag (tmpr4) are validated and the maskable interrupt (intwdt) can be generated. among maskable interrupts, the intwdt default has the highest priority. the interval timer continues operating in the halt mode but it stops in stop mode. thus, set run to 1 before the stop mode is set, clear the interval timer and then execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless reset input is applied. 2. the interval time just after setting with wdtm may be shorter than the set time by a maximum of 0.5 %. 3. when the subsystem clock is selected for cpu clock, watchdog timer count operation is stopped. table 11-5. interval timer interval time tcl22 tcl21 tcl20 interval time mcs = 1 mcs = 0 000 2 11 1/f xx 2 11 1/f x (410 m s) 2 12 1/f x (819 m s) 001 2 12 1/f xx 2 12 1/f x (819 m s) 2 13 1/f x (1.64 ms) 010 2 13 1/f xx 2 13 1/f x (1.64 ms) 2 14 1/f x (3.28 ms) 011 2 14 1/f xx 2 14 1/f x (3.28 ms) 2 15 1/f x (6.55 ms) 100 2 15 1/f xx 2 15 1/f x (6.55 ms) 2 16 1/f x (13.1 ms) 101 2 16 1/f xx 2 16 1/f x (13.1 ms) 2 17 1/f x (26.2 ms) 110 2 17 1/f xx 2 17 1/f x (26.2 ms) 2 18 1/f x (52.4 ms) 111 2 19 1/f xx 2 19 1/f x (104.9 ms) 2 20 1/f x (209.7 ms) remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs : oscillation mode selection register bit 0 4. figures in parentheses apply to operation with f x = 5.0 mhz.
209 users manual u10105ej4v1um00 chapter 12 clock output control circuit 12.1 clock output control circuit functions the clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral lsi. clocks selected with the timer clock select register 0 (tcl0) are output from the pcl/p35 pin. follow the procedure below to output clock pulses. (1) select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (tcl00 to tcl03) of tcl0. (2) set the p35 output latch to 0. (3) set bit 5 (pm35) of port mode register 3 to 0 (set to output mode). (4) set bit 7 (cloe) of timer clock select register 0 to 1. caution clock output cannot be used when setting p35 output latch to 1. remark when clock output enable/disable is switched, the clock output control circuit does not output pulses with small widths (see the portions marked with * in figure 12-1 ). figure 12-1. remote controlled output application example cloe pcl/p35 pin output **
210 chapter 12 clock output control circuit users manual u10105ej4v1um00 12.2 clock output control circuit configuration the clock output control circuit consists of the following hardware. table 12-1. clock output control circuit configuration item configuration timer clock select register 0 (tcl0) port mode register 3 (pm3) figure 12-2. clock output control circuit block diagram control register internal bus f xx f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xt cloe tcl03 tcl02 tcl01 tcl00 p35 output latch synchronizing circuit 4 pm35 selector timer clock select register 0 port mode register 3 pcl /p35
211 chapter 12 clock output control circuit users manual u10105ej4v1um00 12.3 clock output function control registers the following two types of registers are used to control the clock output function. ? timer clock select register 0 (tcl0) ? port mode register 3 (pm3) (1) timer clock select register 0 (tcl0) this register sets pcl output clock. tcl0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tcl0 to 00h. remark besides setting pcl output clock, tcl0 sets the 16-bit timer register count clock. cautions 1. setting of the ti00/intp0 pin valid edge is performed by external interrupt mode register 0, and selection of the sampling clock frequency is performed by the sampling clock selection register. 2. when enabling pcl output, set tcl00 to tcl03, then set 1 in cloe with a 1-bit memory manipulation instruction. 3. to read the count value when ti00 has been specified as the tm0 count clock, the value should be read from tm0, not from capture/compare register 01 (cr01). 4. when rewriting tcl0 to other data, stop the timer operation beforehand.
212 chapter 12 clock output control circuit users manual u10105ej4v1um00 figure 12-3. timer clock select register 0 format remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. ti00 : 16-bit timer/event counter input pin 5. tm0 : 16-bit timer register 6. mcs : oscillation mode selection register bit 0 7. figures in parentheses apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. cloe 7 tcl06 6 tcl05 tcl04 4 tcl03 3210 ff40h address tcl0 symbol tcl02 tcl01 tcl00 5 00h after reset r/w r/w 0 0 0 0 1 1 1 1 1 other than above 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 tcl03 tcl02 tcl01 f xt (32.768 khz) f xx f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 setting prohibited mcs=1 f x (5.0 mhz) f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) mcs=0 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) pcl output clock selection cloe 0 1 pcl output control output disable output enable 0 0 0 0 1 1 other than above 0 0 1 1 0 1 0 1 0 1 0 1 tcl06 tcl05 tcl04 ti00 (valid edge specifiable) 2f xx f xx f xx /2 f xx /2 2 watch timer output (inttm3) setting prohibited mcs=1 setting prohibited f x (5.0 mhz) f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) mcs=0 f x (5.0 mhz) f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 16-bit timer register count clock selection tcl00 0 1 0 1 0 1 0 1 0
213 chapter 12 clock output control circuit users manual u10105ej4v1um00 (2) port mode register 3 (pm3) this register set port 3 input/output in 1-bit units. when using the p35/pcl pin for clock output function, set pm35 and output latch of p35 to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 12-4. port mode register 3 format pm37 7 pm36 6 pm35 pm34 4 pm33 3210 ff23h address pm3 symbol pm32 pm31 pm30 5 ffh after reset r/w r/w pm3n 0 1 p3n pin input/output mode selection (n=0 to 7) output mode (output buffer on) input mode (output buffer off)
214 users manual u10105ej4v1um00 [memo]
215 users manual u10105ej4v1um00 chapter 13 buzzer output control circuit 13.1 buzzer output control circuit functions the buzzer output control circuit outputs 1.2 khz, 2.4 khz, 4.9 khz, or 9.8 khz frequency square waves. the buzzer frequency selected with timer clock select register 2 (tcl2) is output from the buz/p36 pin. follow the procedure below to output the buzzer frequency. (1) select the buzzer output frequency with bits 5 to 7 (tcl25 to tcl27) of tcl2. (2) set the p36 output latch to 0. (3) set bit 6 (pm36) of port mode register 3 to 0 (set to output mode). caution buzzer output cannot be used when setting p36 output latch to 1. 13.2 buzzer output control circuit configuration the buzzer output control circuit consists of the following hardware. table 13-1. buzzer output control circuit configuration item configuration timer clock select register 2 (tcl2) port mode register 3 (pm3) figure 13-1. buzzer output control circuit block diagram control register internal bus f xx /2 9 f xx /2 10 f xx /2 11 tcl27 tcl26 tcl25 3 pm36 selector timer clock select register 2 port mode register 3 buz/p36 p36 output latch
216 chapter 13 buzzer output control circuit users manual u10105ej4v1um00 13.3 buzzer output function control registers the following two types of registers are used to control the buzzer output function. ? timer clock select register 2 (tcl2) ? port mode register 3 (pm3) (1) timer clock select register 2 (tcl2) this register sets the buzzer output frequency. tcl2 is set with an 8-bit memory manipulation instruction. reset input sets tcl2 to 00h. remark besides setting the buzzer output frequency, tcl2 sets the watch timer count clock and the watchdog timer count clock.
217 chapter 13 buzzer output control circuit users manual u10105ej4v1um00 figure 13-2. timer clock select register 2 format caution when rewriting tcl2 to other data, stop the timer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. : don't care 5. mcs : oscillation mode selection register bit 0 6. figures in parentheses apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. tcl27 7 tcl26 6 tcl25 tcl24 4 0 3210 ff42h address tcl2 symbol tcl22 tcl21 tcl20 5 00h after reset r/w r/w 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 tcl22 tcl21 tcl20 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 f xx /2 9 f xx /2 11 mcs=1 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 11 mcs=0 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 10 f x /2 12 watchdog timer count clock selection 0 1 tcl24 f xx /2 7 f xt (32.768 khz) mcs=1 f x /2 7 (39.1 khz) mcs=0 f x /2 8 (19.5 khz) watch timer count clock selection 0 1 1 1 1 0 0 1 1 0 1 0 1 tcl27 tcl26 tcl25 buzzer output disable f xx /2 9 f xx /2 10 f xx /2 11 setting prohibited mcs=1 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) mcs=0 f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) f x /2 12 (1.2 khz) buzzer output frequency selection (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) (9.8 khz) (2.4 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) (9.8 khz) (4.9 khz) (1.2 khz)
218 chapter 13 buzzer output control circuit users manual u10105ej4v1um00 (2) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p36/buz pin for buzzer output function, set pm36 and output latch of p36 to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 13-3. port mode register 3 format pm37 7 pm36 6 pm35 pm34 4 pm33 3210 ff23h address pm3 symbol pm32 pm31 pm30 5 ffh after reset r/w r/w pm3n 0 1 p3n pin input/output mode selection (n=0 to 7) output mode (output buffer on) input mode (output buffer off)
219 users manual u10105ej4v1um00 chapter 14 a/d converter 14.1 a/d converter functions the a/d converter converts an analog input into a digital value. it consists of 8 channels (ani0 to ani7) with an 8-bit resolution. the conversion method is based on successive approximation and the conversion result is held in the 8-bit a/d conversion result register (adcr). the following two ways are available to start a/d conversion. (1) hardware start conversion is started by trigger input (intp3). (2) software start conversion is started by setting the a/d converter mode register. one channel of analog input is selected from ani0 to ani7 and a/d conversion is carried out. in the case of hardware start, a/d conversion operation stops when an a/d conversion operation ends. in the case of software start, the a/d conversion operation is repeated. each time an a/d conversion operation ends, an interrupt request (intad) is generated. 14.2 a/d converter configuration the a/d converter consists of the following hardware. table 14-1. a/d converter configuration item configuration analog input 8 channels (ani0 to ani7) a/d converter mode register (adm) control register a/d converter input select register (adis) external interrupt mode register 1 (intm1) successive approximation register (sar) a/d conversion result register (adcr) register
220 chapter 14 a/d converter users manual u10105ej4v1um00 figure 14-1. a/d converter block diagram notes 1. selector to select the number of channels to be used for analog input. 2. selector to select the channel for a/d conversion. * ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 selector a /d converter mode register 3 trigger enable es40, es41 sample & hold circuit 3 cs 4 internal bus internal bus edge detector control circuit series resistor string av dd voltage comparator tap selector intad intp3 successive approximation register (sar) note 1 note 2 adm1-adm3 intp3/p03 trg fr1 fr0 adm3 adm2 adm1 a / d conversion result register (adcr) av ref av ss adis3 a/d converter input select register adis2 adis1 adis0 selector
221 chapter 14 a/d converter users manual u10105ej4v1um00 (1) successive approximation register (sar) this register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (msb). when up to the least significant bit (lsb) is set (termination of a/d conversion), the sar contents are transferred to the a/d conversion result register. (2) a/d conversion result register (adcr) this register holds the a/d conversion result. each time a/d conversion terminates, the conversion result is loaded from the successive approximation register. adcr is read with an 8-bit memory manipulation instruction. reset input makes adcr undefined. (3) sample & hold circuit the sample & hold circuit samples each analog input sequentially applied from the input circuit and sends it to the voltage comparator. this circuit holds the sampled analog input voltage value during a/d conversion. (4) voltage comparator the voltage comparator compares the analog input to the series resistor string output voltage. (5) series resistor string the series resistor string is in av ref to av ss and generates a voltage to be compared to the analog input. (6) ani0 to ani7 pins these are 8-channel analog input pins to input analog signals to undergo a/d conversion to the a/d converter. pins other than those selected as analog input by the a/d converter input select register (adis) can be used as input/output ports. caution use ani0 to ani7 input voltages within the specified range. if a voltage higher than av ref or lower than av ss is applied (even if within the absolute maximum ratings), the converted value of the corresponding channel becomes indeterminate and may adversely affect the converted values of other channels. (7) av ref pin this pin inputs the a/d converter reference voltage. it converts signals input to ani0 to ani7 into digital signals according to the voltage applied between av ref and av ss . the current flowing in the series resistor string can be reduced by setting the voltage to be input to the av ref pin to av ss level in standby mode. (8) av ss pin this is a gnd potential pin of the a/d converter. keep it at the same potential as the v ss pin when not using the a/d converter. (9) av dd pin this is an a/d converter analog power supply pin. keep it at the same potential as the v ss pin when not using the a/d converter.
222 chapter 14 a/d converter users manual u10105ej4v1um00 14.3 a/d converter control registers the following three types of registers are used to control the a/d converter. ? a/d converter mode register (adm) ? a/d converter input select register (adis) ? external interrupt mode register 1 (intm1) (1) a/d converter mode register (adm) this register sets the analog input channel for a/d conversion, conversion time, conversion start/stop and external trigger. adm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets adm to 01h.
223 chapter 14 a/d converter users manual u10105ej4v1um00 figure 14-2. a/d converter mode register format notes 1. set so that the a/d conversion time is 19.1 m s or more. 2. setting prohibited because a/d conversion time is less than 19.1 m s. cautions 1. the following sequence is recommended for power consumption reduction of a/d converter when the standby function is used: clear bit 7 (cs) to 0 first to stop the a/d conversion operation, and then execute the halt or stop instruction. 2. when restarting the stopped a/d conversion operation, start the a/d conversion operation after clearing the interrupt request flag (adif) to 0. remarks 1. f x : main system clock oscillation frequency 2. mcs : oscillation mode selection register bit 0 * cs 7 trg 6 fr1 fr0 4 adm3 3210 ff80h address adm symbol adm2 adm1 hsc 5 01h after reset r/w r/w adm3 0 0 0 0 1 1 1 1 adm2 0 0 1 1 0 0 1 1 adm1 0 1 0 1 0 1 0 1 analog input channel selection ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 trg 0 1 external trigger selection no external trigger (software starts) conversion started by external trigger (hardware starts) fr1 0 0 1 1 fr0 0 1 0 0 a/d conversion time selection note 1 f x =5.0 mhz operation mcs=1 80/f x ( setting prohibited note 2 ) 40/f x ( setting prohibited note 2 ) 50/f x ( setting prohibited note 2 ) 100/f x (20.0 s) setting prohibited m mcs=0 160/f x (32.0 s) 80/f x ( setting prohibited note 2 ) 100/f x (20.0 s) 200/f x (40.0 s) f x =4.19 mhz operation mcs=1 80/f x (19.1 s) 40/f x ( setting prohibited note 2 ) 50/f x ( setting prohibited note 2 ) 100/f x (23.8 s) mcs=0 160/f x (38.1 s) 80/f x (19.1 s) 100/f x (23.8 s) 200/f x (47.7 s) m m m m m m m cs 0 1 a/d conversion operation control operation stop operation start hsc 1 1 0 1 m m other than above
224 chapter 14 a/d converter users manual u10105ej4v1um00 (2) a/d converter input select register (adis) this register determines whether the ani0/p10 to ani7/p17 pins should be used for analog input channels or ports. pins other than those selected as analog input can be used as input/output ports. adis is set with an 8-bit memory manipulation instruction. reset input sets adis to 00h. cautions 1. set the analog input channel in the following order. (1) set the number of analog input channels with adis. (2) using adm, select one channel to undergo a/d conversion from among the channels set for analog input with adis. 2. no internal pull-up resistor can be connected to the channels set for analog input with adis, irrespective of the value of bit 1 (puo1) of the pull-up resistor option register l. figure 14-3. a/d converter input select register format 0 7 0 6 00 4 adis3 3210 ff84h address adis symbol adis2 adis1 adis0 5 00h after reset r/w r/w adis3 0 0 0 0 0 0 0 0 1 other than above number of analog input channel selection no analog input channel (p10-p17) 1 channel (ani0, p11-p17) 2 channel (ani0, ani1, p12-p17) 3 channel (ani0-ani2, p13-p17) 4 channel (ani0-ani3, p14-p17) 5 channel (ani0-ani4, p15-p17) 6 channel (ani0-ani5, p16, p17) 7 channel (ani0-ani6, p17) 8 channel (ani0-ani7) setting prohibited adis2 0 0 0 0 1 1 1 1 0 adis1 0 0 1 1 0 0 1 1 0 adis0 0 1 0 1 0 1 0 1 0
225 chapter 14 a/d converter users manual u10105ej4v1um00 (3) external interrupt mode register 1 (intm1) this register sets the valid edge for intp3 to intp5. intm1 is set with an 8-bit memory manipulation instruction. reset input sets intm1 to 00h. figure 14-4. external interrupt mode register 1 format 0 7 0 6 es61 es60 4 es51 3210 ffedh address intm1 symbol es50 es41 es40 5 00h after reset r/w r/w es41 0 0 1 1 es40 0 1 0 1 intp3 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es51 0 0 1 1 es50 0 1 0 1 intp4 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es61 0 0 1 1 es60 0 1 0 1 intp5 valid edge selection falling edge rising edge setting prohibited both falling and rising edges
226 chapter 14 a/d converter users manual u10105ej4v1um00 14.4 a/d converter operations 14.4.1 basic operations of a/d converter (1) set the number of analog input channels with a/d converter input select register (adis). (2) from among the analog input channels set with adis, select one channel for a/d conversion with a/d converter mode register (adm). (3) sample the voltage input to the selected analog input channel with the sample & hold circuit. (4) sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit holds the input analog voltage until termination of a/d conversion. (5) bit 7 of the successive approximation register (sar) is set and the tap selector sets the series resistor string voltage tap to (1/2) av ref . (6) the voltage difference between the series resistor string voltage tap and analog input is compared with a voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set. if the input is smaller than (1/2) av ref , the msb is reset. (7) next, bit 6 of sar is automatically set and the operation proceeds to the next comparison. in this case, the series resistor string voltage tap is selected according to the preset value of bit 7 as described below. ? bit 7 = 1 : (3/4) av ref ? bit 7 = 0 : (1/4) av ref the voltage tap and analog input voltage are compared and bit 6 of sar is manipulated with the result as follows. ? analog input voltage 3 voltage tap : bit 6 = 1 ? analog input voltage voltage tap : bit 6 = 0 (8) comparison of this sort continues up to bit 0 of sar. (9) upon completion of the comparison of 8 bits, any effective digital resultant value remains in sar and the resultant value is transferred to and latched in the a/d conversion result register (adcr). at the same time, the a/d conversion termination interrupt request (intad) can also be generated.
227 chapter 14 a/d converter users manual u10105ej4v1um00 figure 14-5. a/d converter basic operation a/d conversion operations are performed continuously until the cs bit is reset (0) by software. if a write to the adm register is performed during an a/d conversion operation, the conversion operation is initialized, and if the cs bit is set (1), conversion starts again from the beginning. after reset input, the value of adcr is undefined. sar adcr intad a/d converter operation sampling time sampling a /d conversion conversion time undefined 80h c0h or 40h conversion result conversion result
228 chapter 14 a/d converter users manual u10105ej4v1um00 14.4.2 input voltage and conversion results the relation between the analog input voltage input to the analog input pins (ani0 to ani7) and the a/d conversion result (the value stored in adcr) is shown by the following expression. adcr = int ( 256 + 0.5) or (adcr C 0.5) v in < (adcr + 0.5) int( ) : function which returns integer parts of value in parentheses. v in : analog input voltage av ref :av ref pin voltage adcr : adcr register value figure 14-6 shows the relation between the analog input voltage and the a/d conversion result. figure 14-6. relations between analog input voltage and a/d conversion result v in av ref av ref 256 av ref 256 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 255 254 253 3 2 1 0 a/d conversion results (adcr) input voltage/av ref
229 chapter 14 a/d converter users manual u10105ej4v1um00 14.4.3 a/d converter operating mode the operating mode is a select mode. one analog input channel is selected from among ani0 to ani7 with the a/d converter input select register (adis) and a/d converter mode register (adm) and a/d conversion is executed. the following two ways are available to start a/d conversion. ? hardware start: conversion is started by trigger input (intp3). ? software start: conversion is started by setting adm. the a/d conversion result is stored in the a/d conversion result register (adcr) and the interrupt request signal (intad) is simultaneously generated. (1) a/d conversion by hardware start when bit 6 (trg) and bit 7 (cs) of adm are set to 1, the a/d conversion standby state is set. when the external trigger signal (intp3) is input, the a/d conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (adm1 to adm3) of adm. upon termination of the a/d conversion, the conversion result is stored in the a/d conversion result register (adcr) and the interrupt request signal (intad) is generated. after one a/d conversion operation is started and terminated, another operation is not started until a new external trigger signal is input. if data with cs set to 1 is written to adm again during a/d conversion, the converter suspends its a/d conversion operation and waits for a new external trigger signal to be input. when the external trigger input signal is reinput, a/d conversion is carried out from the beginning. if data with cs set to 0 is written to adm during a/d conversion, the a/d conversion operation stops immediately. figure 14-7. a/d conversion by hardware start remarks 1. n = 0, 1, ... , 7 2. m = 0, 1, ... , 7 adm rewrite cs=1, trg=1 standby state anin intp3 a /d conversion adcr intad anin anin anin anim anim anin anin standby state standby state adm rewrite cs=1, trg=1 anim anim anim
230 chapter 14 a/d converter users manual u10105ej4v1um00 (2) a/d conversion operation in software start when bit 6 (trg) and bit 7 (cs) of a/d converter mode register (adm) are set to 0 and 1, respectively, the a/d conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (adm1 to adm3) of adm. upon termination of the a/d conversion, the conversion result is stored in the a/d conversion result register (adcr) and the interrupt request signal (intad) is generated. after one a/d conversion operation is started and terminated, the next a/d conversion operation starts immediately. the a/d conversion operation con- tinues repeatedly until new data is written to adm. if data with cs set to 1 is written to adm again during a/d conversion, the converter suspends its a/d conversion operation and starts a/d conversion on the newly written data. if data with cs set to 0 is written to adm during a/d conversion, the a/d conversion operation stops im- mediately. figure 14-8. a/d conversion by software start remarks 1. n = 0, 1, ... , 7 2. m = 0, 1, ... , 7 conversion start cs=1, trg=0 a /d conversion adcr intad anin anin anim anin anim anim anin anin adm rewrite cs=1, trg=0 adm rewrite cs=0, trg=0 conversion suspended conversion results are not stored stop
231 chapter 14 a/d converter users manual u10105ej4v1um00 14.5 a/d converter cautions (1) current consumption in standby mode the a/d converter operates on the main system clock. therefore, its operation stops in stop mode or in halt mode with the subsystem clock. as a current still flows in the av ref pin at this time, this current must be cut in order to minimize the overall system power dissipation. in figure 14-9, the power dissipation can be reduced by outputting a low-level signal to the output port in standby mode. however, there is no precision to the actual av ref voltage, and therefore the conversion values themselves lack precision and can only be used for relative comparison. figure 14-9. example of method of reducing current consumption in standby mode (2) input range of ani0 to ani7 the input voltages of ani0 to ani7 should be within the specification range. in particular, if a voltage above av ref or below av ss is input (even if within the absolute maximum rating range), the conversion value for that channel will be indeterminate. the conversion values of the other channels may also be affected. series resistor string v dd av ref av ss output port av ref =v dd . . m pd78064, 78064y
232 chapter 14 a/d converter users manual u10105ej4v1um00 (3) noise countermeasures in order to maintain 8-bit resolution, attention must be paid to noise on pins av ref and ani0 to ani7. since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in figure 14-10 in order to reduce noise. figure 14-10. analog input pin disposition (4) pins ani0/p10 to ani7/p17 the analog input pins ani0 to ani7 also function as input/output port (port1) pins. when a/d conversion is performed with any of pins ani0 to ani7 selected, be sure not to execute a port1 input instruction while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. (5) av ref pin input impedance a series resistor string of approximately 10 k w is connected between the av ref pin and the av ss pin. therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the av ref pin and the av ss pin, and there will be a large reference voltage error. ani0-ani7 av ref v dd av dd av ss v ss reference voltage input c=100-1000 pf if there is possibility that noise whose level is av ref or higher or av ss or lower may enter, clamp with a diode with a small v f (0.3 v or less). v dd
233 chapter 14 a/d converter users manual u10105ej4v1um00 (6) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the a/d converter mode register (adm) is changed. caution is therefore required since, if a change of analog input pin is performed during a/d conversion, the a/d conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the adm rewrite, and when adif is read immediately after the adm rewrite, adif may be set despite the fact that the a/d conversion for the post-change analog input has not ended. when the a/d conversion is stopped and then resumed, clear the interrupt request flag (adif) before it is resumed. figure 14-11. a/d conversion end interrupt generation timing (7) av dd pin the av dd pin is the analog circuit power supply pin, and supplies power to the input circuits of ani0/p10 to ani7/p17. therefore, be sure to apply the same voltage as v dd to this pin even when the application circuit is designed so as to switch to a backup battery. figure 14-12. handling of av dd pin a /d conversion adcr intad anin anin anim anim anin anin anim anim adm rewrite (start of anin conversion) adm rewrite (start of anim conversion) adif is set but anim conversion has not ended main power supply av ref v dd av dd av ss v ss capacitor for back-up *
234 users manual u10105ej4v1um00 [memo]
235 users manual u10105ej4v1um00 chapter 15 serial interface channel 0 ( m pd78064 subseries) the m pd78064 subseries incorporates two channels of serial interfaces. differences between channels 0 and 2 are as follows (refer to chapter 17 serial interface channel 2 for details of the serial interface channel 2). table 15-1. differences between channels 0 and 2 serial transfer mode channel 0 f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xx /2 8 , external clock, to2 output msb/lsb switchable as the start bit serial transfer end interrupt request flag (csiif0) clock selection transfer method transfer end flag sbi (serial bus interface) 2-wire serial i/o uart (asynchronous serial interface) use possible none 3-wire serial i/o channel 2 external clock, baud rate generator output msb/lsb switchable as the start bit serial transfer end interrupt request flag (srif) none use possible
236 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 15.1 serial interface channel 0 functions serial interface channel 0 employs the following four modes. ? operation stop mode ? 3-wire serial i/o mode ? sbi (serial bus interface) mode ? 2-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not carried out. power consumption can be reduced. (2) 3-wire serial i/o mode (msb-/lsb-first selectable) this mode is used for 8-bit data transfer using three lines, one each for serial clock (sck0), serial output (so0) and serial input (si0). this mode enables simultaneous transmission/reception and therefore reduces the data transfer processing time. the start bit of transferred 8-bit data is switchable between msb and lsb, so that devices can be connected regardless of their start bit recognition. this mode should be used when connecting with peripheral i/o devices or display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75x, 78k, and 17k series. (3) sbi (serial bus interface) mode (msb-first) this mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (sck0) and serial data bus (sb0 or sb1). the sbi mode is in compliance with the nec serial bus format. in the sbi mode, the transmitter outputs three kinds of data onto the serial data bus: addresses to selct a device to be communicated with, commands to give instructions to the selected device, and data to be actually sent or received. the receiver automatically distinguishes the received data into address, command, or data, by hardware. this function enables the input/output ports to be used effectively and the application program serial interface control portions to be simplified. in this mode, the wake-up function for handshake and the output function of acknowledge and busy signals can also be used.
237 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (4) 2-wire serial i/o mode (msb-first) this mode is used for 8-bit data transfer using two lines of serial clock (sck0) and serial data bus (sb0 or sb1). this mode enables to cope with any one of the possible data transfer formats by controlling the sck0 level and the sb0 or sb1 output level. thus, the handshake line previously necessary for connection of two or more devices can be removed, resulting in the increased number of available input/output ports. figure 15-1. serial bus interface (sbi) system configuration example master cpu sck0 sb0 sck0 sb0 slave cpu1 sck0 sb0 slave cpu2 sck0 sb0 slave cpun v dd
238 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 15.2 serial interface channel 0 configuration serial interface channel 0 consists of the following hardware. table 15-2. serial interface channel 0 configuration item configuration serial i/o shift register 0 (sio0) slave address register (sva) timer clock select register 3 (tcl3) serial operating mode register 0 (csim0) control register serial bus interface control register (sbic) interrupt timing specify register (sint) port mode register 2 (pm2) register
239 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 p25 output latch csie0 coi wup csim 04 csim 03 csim 02 csim 01 csim 00 serial operating mode register 0 control circuit output control selector si0/sb0/ p25 pm25 output control so0/sb1/ p26 pm26 output control sck0/ p27 pm27 selector p26 output latch cld p27 output latch internal bus internal bus bus release/ command/ acknowledge detector serial clock counter serial clock control circuit clr d set q match busy/ acknowledge output circuit interrupt request signal generator ackd cmdd reld wup selector selector f xx /2-f xx /2 8 intcsi0 bsye ackd acke ackt cmdd reld cmdt relt cld sic svam csim01 csim00 csim01 csim00 slave address register (sva) serial i/o shift register 0 (sio0) to2 interrupt timing specify register tcl33 tcl32 tcl31 tcl30 4 timer clock select register 3 serial bus interface control register svam figure 15-2. serial interface channel 0 block diagram remark output control performs selection between cmos output and n-ch open drain output.
240 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (1) serial i/o shift register 0 (sio0) this is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. sio0 is set with an 8-bit memory manipulation instruction. when bit 7 (csie0) of serial operating mode register 0 (csim0) is 1, writing data to sio0 starts serial operation. in transmission, data written to sio0 is output to the serial output (so0) or serial data bus (sb0/sb1). in reception, data is read from the serial input (si0) or sb0/sb1 to sio0. note that, if a bus is driven in the sbi mode or 2-wire serial i/o mode, the bus pin must serve for both input and output. thus, in the case of a device for reception, write ffh to sio0 in advance (except when address reception is carried out by setting bit 5 (wup) of csim0 to 1). in the sbi mode, the busy state can be cleared by writing data to sio0. in this case, bit 7 (bsye) of the serial bus interface control register (sbic) is not cleared to 0. reset input makes sio0 undefined. (2) slave address register (sva) this is an 8-bit register to set the slave address value for connection of a slave device to the serial bus. sva is set with an 8-bit memory manipulation instruction. the master device outputs a slave address for selection of a particular slave device to the connected slave device. these two data (the slave address output from the master device and the sva value) are compared with an address comparator. if they match, the slave device has been selected. in that case, bit 6 (coi) of serial operating mode register 0 (csim0) becomes 1. address comparison can also be executed on the data of lsb-masked high-order 7 bits with bit 4 (svam) of the interrupt timing specify register (sint). if no matching is detected in address reception, bit 2 (reld) of the serial bus interface control register (sbic) is cleared to 0. when bit 5 (wup) of csim0 is 1, the interrupt request signal (intcsi0) is generated only if the matching is detected. this interrupt request enables to recognize the generation of the communication request from the master device. further, when sva transmits data as master or slave device in the sbi or 2-wire serial i/o mode, errors are detected if any. reset input makes sva undefined.
241 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (3) so0 latch this latch holds si0/sb0/p25 and so0/sb1/p26 pin levels. it can be directly controlled by software. in the sbi mode, this latch is set upon termination of the 8th serial clock. (4) serial clock counter this counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received. (5) serial clock control circuit this circuit controls serial clock supply to the serial i/o shift register 0 (sio0). when the internal system clock is used, the circuit also controls clock output to the sck0/p27 pin. (6) interrupt request signal generator this circuit controls interrupt request signal generation. it generates the interrupt request signal in the following cases. ? in the 3-wire serial i/o mode and 2-wire serial i/o mode this circuit generates an interrupt request signal every eight serial clocks. ? in the sbi mode when wup is 0 ........... generates an interrupt request signal every eight serial clocks. when wup is 1 ........... generates an interrupt request signal when the serial i/o shift register 0 (sio0) value matches the slave address register (sva) value after address reception. remark wup is wake-up function specify bit. it is bit 5 of serial operating mode register 0 (csim0). (7) busy/acknowledge output circuit and bus release/command/acknowledge detector these two circuits output and detect various control signals in the sbi mode. these do not operate in the 3-wire serial i/o mode and 2-wire serial i/o mode.
242 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 15.3 serial interface channel 0 control registers the following four types of registers are used to control serial interface channel 0. ? timer clock select register 3 (tcl3) ? serial operating mode register 0 (csim0) ? serial bus interface control register (sbic) ? interrupt timing specify register (sint) (1) timer clock select register 3 (tcl3) this register sets the serial clock of serial interface channel 0. tcl3 is set with an 8-bit memory manipulation instruction. reset input sets tcl3 to 88h.
243 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 figure 15-3. timer clock select register 3 format cautions 1. set bit 4 to bit 6 to 0, and bit 7 to 1. 2. when rewriting tcl3 to other data, stop the serial transfer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs : oscillation mode selection register bit 0 4. figures in parentheses apply to operation with f x = 5.0 mhz. serial interface channel 0 serial clock selection tcl33 tcl32 tcl31 tcl30 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 mcs = 1 setting prohibited f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) mcs = 0 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) other than above setting prohibited 6543210 7 symbol tcl3 1 0 0 0 tcl33 tcl32 tcl31 tcl30 ff43h 88h r/w address after reset r/w
244 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (2) serial operating mode register 0 (csim0) this register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. figure 15-4. serial operating mode register 0 format (1/2) notes 1. bit 6 (coi) is a read-only bit. 2. can be used as p25 (cmos input/output) when used only for transmission. 3. can be used freely as port function. remark : dont care sbi mode 6543210 7 symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output 0 0 sck0 (cmos input/output) r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 1 csim00 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit sio/sb0/p25 pin function so0/sb1/p26 pin function sck0/p27 pin function 10 0 0 0 0 0 0 1 1 note 3 note 3 note 3 note 3 msb p25 (cmos input/output) sb0 (n-ch open-drain input/output) sb1 (n-ch open-drain input/output) p26 (cmos input/output) 1 msb lsb 1 0001 note 2 3-wire serial l/o mode si0 (input) so0 (cmos output) sck0 (cmos input/output) note 2 2-wire serial l/o mode 0 sck0 (n-ch open-drain input/output) 1 11 0 0 0 0 0 0 1 1 note 3 note 3 note 3 note 3 msb p25 (cmos input/output) sb0 (n-ch open-drain input/output) sb1 (n-ch open-drain input/output) p26 (cmos input/output) note 2 *
245 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 figure 15-4. serial operating mode register 0 format (2/2) note when csie0 = 0, coi becomes 0. wup 0 1 wake-up function control interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after bus release (when cmdd = reld = 1) matches the slave address register data in sbi mode r/w coi 0 1 slave address comparison result flag note slave address register not equal to serial i/o shift register 0 data slave address register equal to serial i/o shift register 0 data r csie0 0 1 serial interface channel 0 operation control operation stopped operation enable r/w
246 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (3) serial bus interface control register (sbic) this register sets serial bus interface operation and displays statuses. sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic to 00h. figure 15-5. serial bus interface control register format (1/2) note bits 2, 3, and 6 (reld, cmdd and ackd) are read-only bits. remark bits 0, 1, and 4 (reld, cmdt, and ackt) are 0 when read after data setting. 6543210 7 symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt used for bus release signal output. when relt = 1, so iatch is set to 1. after so latch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w note address after reset r/w cmdt used for command signal output. when cmdt = 1, so iatch is cleared to (0). after so latch clearance, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w r reld bus release detection set conditions (reld =1) clear conditions (reld = 0) ?when bus release signal (rel) is detected ?when transfer start instruction is executed ?if sio0 and sva values do not match in address reception ?when csie0 = 0 ?when reset input is applied r cmdd command detection clear conditions (cmdd = 0) ?when transfer start instruction is executed ?when bus release signal (rel) is detected ?when csie0 = 0 ?when reset input is applied set conditions (cmdd = 1) ?when command signal (cmd) is detected ackt acknowledge signal is output in synchronization with the falling edge clock of sck0 just after execution of the instruction to be set to 1, and after acknowledge signal output, automatically cleared to 0. used as acke=0. also cleared to 0 upon start of serial interface transfer or when csie0 = 0. r/w
247 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 figure 15-5. serial bus interface control register format (2/2) note the busy mode can be canceled by start of serial interface transfer or reception of address signal. however, the bsye flag is not cleared to 0. acke acknowledge signal output control 0 acknowledge signal automatic output disable (output with ackt enable) acknowledge signal is output in synchronization with the 9th clock falling edge of sck0 (automatically output when acke = 1). before completion of transfer acknowledge signal is output in synchronization with the falling edge of sck0 just after execution of the instruction to be set to 1 (automatically output when acke = 1). however, not automatically cleared to 0 after acknowledge signal output. after completion of transfer 1 r/w r ackd acknowledge detection clear conditions (ackd = 0) ?falling edge of the sck0 immediately after the busy mode is released while executing the transfer start instruction ?when csie0 = 0 ?when reset input is applied set conditions (ackd = 1) ?when acknowledge signal (ack) is detected at the rising edge of sck0 clock after completion of transfer bsye synchronizing busy signal output control 0 disables busy signal which is output in synchronization with the falling edge of sck0 clock just after execution of the instruction to be cleared to 0. r/w note 1 outputs busy signal at the falling edge of sck0 clock following the acknowledge signal.
248 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (4) interrupt timing specify register (sint) this register sets the bus release interrupt and address mask functions and displays the sck0 pin level status. sint is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sint to 00h. figure 15-6. interrupt timing specify register format notes 1. bit 6 (cld) is a read-only bit. 2. when using wake-up function in the sbi mode, set sic to 0. 3. when csie0 = 0, cld becomes 0. caution be sure to set bit 0 to bit 3 to 0. remark sva : slave address register 6543210 7 symbol sint 0 cld sic svam 0 0 0 0 ff63h 00h r/w note 1 address after reset r/w svam 0 1 sva bit to be used as slave address bits 0 to 7 bits 1 to 7 sic 0 intcsi0 interrupt cause selection note 2 csiif0 is set upon termination of serial interface channel 0 transfer csiif0 is set upon bus release detection or termination of serial interface channel 0 transfer cld 0 1 sck0 pin level note 3 low level high level r/w r/w r 1
249 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 15.4 serial interface channel 0 operations the following four operating modes are available to the serial interface channel 0. ? operation stop mode ? 3-wire serial i/o mode ? sbi mode ? 2-wire serial i/o mode 15.4.1 operation stop mode serial transfer is not carried out in the operation stop mode. thus, power consumption can be reduced. the serial i/o shift register 0 (sio0) does not carry out shift operation either and thus it can be used as ordinary 8-bit register. in the operation stop mode, the p25/si0/sb0, p26/so0/sb1 and p27/sck0 pins can be used as ordinary input/ output ports. (1) register setting the operation stop mode is set with the serial operating mode register 0 (csim0). csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. the shaded area is used in the operation stop mode. 6543210 7 symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 ff60h 00h r/w address after reset r/w csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1
250 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 15.4.2 3-wire serial i/o mode operation the 3-wire serial i/o mode is valid for connection of peripheral i/o units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75x, 78k, and 17k series. communication is carried out with three lines of serial clock (sck0), serial output (so0), and serial input (si0). (1) register setting the 3-wire serial i/o mode is set with the serial operating mode register 0 (csim0) and serial bus interface control register (sbic). (a) serial operating mode register 0 (csim0) csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. the shaded area is used in the 3-wire serial i/o mode. *
251 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 notes 1. bit 6 (coi) is a read-only bit. 2. can be used as p25 (cmos input/output) when used only for transmission. 3. be sure to set wup to 0 when the 3-wire serial i/o mode is selected. remark : dont care 6543210 7 symbol csim0 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output 0 sbi mode (see section 15.4.3, ?bi mode operation?) r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 csim00 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit sio/sb0/p25 pin function so0/sb1/p26 pin function sck0/p27 pin function 10 wup 0 1 wake-up function control interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after bus release (when cmdd=reld=1) matches the slave address register data in sbi mode r/w 1 msb lsb 1 0001 note 2 3-wire serial l/o mode si0 (input) so0 (cmos output) sck0 (cmos input/output) 2-wire serial i/o mode (see section 15.4.4, ?-wire serial i/o mode operation?) 11 note 2 note 3 note 2 csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 csie0 coi wup csim04 csim03 csim02 csim01 csim00
252 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (b) serial bus interface control register (sbic) sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic to 00h. the shaded area is used in the 3-wire serial i/o mode. 6543210 7 symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt when relt = 1, so iatch is set to 1. after so iatch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w address after reset r/w cmdt when cmdt = 1, so iatch is cleared to 0. after so latch clearance, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w
253 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (2) communication operation the 3-wire serial i/o mode is used for data transmission/reception in 8-bit units. bit-wise data transmission/ reception is carried out in synchronization with the serial clock. shift operation of the serial i/o shift register 0 (sio0) is carried out at the falling edge of the serial clock (sck0). the transmitted data is held in the so0 latch and is output from the so0 pin. the received data input to the si0 pin is latched in sio0 at the rising edge of sck0. upon termination of 8-bit transfer, sio0 operation stops automatically and the interrupt request flag (csiif0) is set. figure 15-7. 3-wire serial i/o mode timings the so0 pin is a cmos output pin and outputs current so0 latch statuses. thus, the so0 pin output status can be manipulated by setting the relt and cmdt bits. however, do not carry out this manipulation during serial transfer. control the sck0 pin output level in the output mode (internal system clock mode) by manipulating the p27 output latch (refer to 15.4.5 sck0/p27 pin output manipulation ). (3) other signals figure 15-8 shows relt and cmdt operations. figure 15-8. relt and cmdt operations si0 sck0 12345678 di7 di6 di5 di4 di3 di2 di1 di0 so0 do7 do6 do5 do4 do3 do2 do1 do0 csiif0 transfer start at the falling edge of sck0 end of transfer relt cmdt so0 latch
254 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (4) msb/lsb switching as the start bit the 3-wire serial i/o mode enables to select transfer to start from msb or lsb. figure 15-9 shows the configuration of the serial i/o shift register 0 (sio0) and internal bus. as shown in the figure, msb/lsb can be read/written in reverse form. msb/lsb switching as the start bit can be specified with bit 2 (csim02) of the serial operating mode register 0 (csim0). figure 15-9. circuit of switching in transfer bit order start bit switching is realized by switching the bit order for data write to sio0. the sio0 shift order remains unchanged. thus, switching between msb-first and lsb-first must be performed before writing data to the shift register. (5) transfer start serial transfer is started by setting transfer data to the serial i/o shift register 0 (sio0) when the following two conditions are satisfied. ? serial interface channel 0 operation control bit (csie0) = 1. ? internal serial clock is stopped or sck0 is a high level after 8-bit serial transfer. caution if csie0 is set to 1 after data write to sio0, transfer does not start. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. 7 6 internal bus 1 0 lsb-first msb-first read/write gate si0 shift register 0 (sio0) read/write gate so0 sck0 dq so0 latch
255 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 15.4.3 sbi mode operation sbi (serial bus interface) is a high-speed serial interface in compliance with the nec serial bus format. sbi uses a single master device and employs the clocked serial i/o format with the addition of a bus configuration function. this function enables devices to communicate using only two lines. thus, when making up a serial bus with two or more microcontrollers and peripheral ics, the number of ports to be used and the number of wires on the board can be decreased. the master device outputs three kinds of data to slave devices on the serial data bus: addresses to select a device to be communicated with, commands to instruct the selected device, and data which is actually required. the slave device can identify the received data into address, command, or data, by hardware. this function enables the application program serial interface (channel 0) control portions to be simplified. the sbi function is incorporated into various devices including 75x-series devices and 78k-series 8-bit and 16- bit single-chip microcontrollers. figure 15-10 shows a serial bus configuration example when a cpu having a serial interface compliant with sbi and peripheral ics are used. in sbi, the sb0 (sb1) serial data bus pin is an open-drain output pin and therefore the serial data bus line behaves in the same way as the wired-or configuration. in addition, a pull-up resistor must be connected to the serial data bus line. when the sbi mode is used, refer to (10) sbi mode precautions (d) described later. figure 15-10. example of serial bus configuration with sbi caution when exchanging the master cpu/slave cpu, a pull-up resistor is necessary for the serial clock line (sck0) as well because serial clock line (skc0) input/output switching is carried out asynchronously between the master and slave cpus. master cpu sck0 sb0 (sb1) sck0 sb0 (sb1) sck0 sb0 (sb1) sck0 sb0 (sb1) slave cpu address 1 slave cpu address 2 slave ic address n serial clock serial data bus v dd
256 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (1) sbi functions in the conventional serial i/o format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge the busy state, because only the data transfer function is available. if these operations are to be controlled by software, the software must be heavily loaded. in sbi, a serial bus can be configured with two signal lines of serial clock sck0 and serial data bus sb0 (sb1). thus, use of sbi leads to reduction in the number of microcontroller ports and that of wirings and routings on the board. the sbi functions are described below. (a) address/command/data identify function serial data is distinguished into addresses, commands, and data. (b) chip select function by address transmission the master executes slave chip selection by address transmission. (c) wake-up function the slave can easily judge address reception (chip select judgment) with the wake-up function (which can be set/reset by software). when the wake-up function is set, the interrupt request signal (intcsi0) is generated upon reception of a match address. thus, when communication is executed with two or more devices, the cpu except the selected slave devices can operate regardless of underway serial communications. (d) acknowledge signal (ack) control function the acknowledge signal to check serial data reception is controlled. (e) busy signal (busy) control function the busy signal to report the slave busy state is controlled.
257 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (2) sbi definition the sbi serial data format and the signals to be used are defined as follows. serial data to be transferred with sbi consists of three kinds of data: address, command, and data. figure 15-11 shows the address, command, and data transfer timings. figure 15-11. sbi transfer timings the bus release signal and the command signal are output by the master device. busy is output by the slave signal. ack can be output by either the master or slave device (normally, the 8-bit data receiver outputs). serial clocks continue to be output by the master device from 8-bit data transfer start to busy reset. sck0 sb0 (sb1) sck0 sb0 (sb1) sck0 sb0 (sb1) 89 9 a7 a0 ack busy c7 c0 ack busy ready 89 d7 d0 ack busy ready address transfer command transfer data transfer bus release signal command signal
258 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (a) bus release signal (rel) the bus release signal is a signal with the sb0 (sb1) line which has changed from the low level to the high level when the sck0 line is at the high level (without serial clock output). this signal is output by the master device. figure 15-12. bus release signal the bus release signal indicates that the master device is going to transmit an address to the slave device. the slave device incorporates hardware to detect the bus release signal. (b) command signal (cmd) the command signal is a signal with the sb0 (sb1) line which has changed from the high level to the low level when the sck0 line is at the high level (without serial clock output). this signal is output by the master device. figure 15-13. command signal the slave device incorporates hardware to detect the command signal. sck0 h sb0 (sb1) sck0 h sb0 (sb1)
259 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (c) address an address is 8-bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device. figure 15-14. addresses 8-bit data following bus release and command signals is defined as an address. in the slave device, this condition is detected by hardware and whether or not 8-bit data matches the own specification number (slave address) is checked by hardware. if the 8-bit data matches the slave address, the slave device has been selected. after that, communication with the master device continues until a release instruction is received from the master device. figure 15-15. slave selection with address sck0 a7 a6 a5 a4 a3 a2 a1 a0 12345678 sb0 (sb1) address command signal bus release signal master slave 1 not selected slave 2 selected slave 3 not selected slave 4 not selected slave 2 address transmission
260 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (d) command and data the master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. figure 15-16. commands figure 15-17. data 8-bit data following a command signal is defined as command data. 8-bit data without command signal is defined as data. command and data operation procedures are allowed to determine by user according to communications specifications. sck0 c7 c6 c5 c4 c3 c2 c1 c0 12345678 sb0 (sb1) command command si g nal sck0 d7 d6 d5 d4 d3 d2 d1 d0 12345678 sb0 (sb1) data
261 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (e) acknowledge signal (ack) the acknowledge signal is used to check serial data reception between transmitter and receiver. figure 15-18. acknowledge signal [when output in synchronization with 11th clock sck0] [when output in synchronization with 9th clock sck0] the acknowledge signal is one-shot pulse to be generated at the falling edge of sck0 after 8-bit data transfer. it can be positioned anywhere and can be synchronized with any clock sck0. after 8-bit data transmission, the transmitter checks whether the receiver has returned the acknowledge signal. if the acknowledge signal is not returned for the preset period of time after data transmission, it can be judged that data reception has not been carried out correctly. sck0 sb0 (sb1) 8 9 10 11 ack 89 ack sck0 sb0 (sb1) *
262 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (f) busy signal (busy) and ready signal (ready) the busy signal is intended to report to the master device that the slave device is preparing for data transmission/reception. the ready signal is intended to report to the master device that the slave device is ready for data transmission/reception. figure 15-19. busy and ready signals in sbi, the slave device notifies the master device of the busy state by setting sb0 (sb1) line to the low level. the busy signal output follows the acknowledge signal output from the master or slave device. it is set/reset at the falling edge of sck0. when the busy signal is reset, the master device automatically terminates the output of sck0 serial clock. when the busy signal is reset and the ready signal is set, the master device can start the next transfer. ready ack sck0 sb0 (sb1) busy 89
263 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (3) register setting the sbi mode is set with the serial operating mode register 0 (csim0), the serial bus interface control register (sbic), and the interrupt timing specify register (sint). (a) serial operating mode register 0 (csim0) csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. the shaded area is used in the sbi mode. * notes 1. bit 6 (coi) is a read-only bit. 2. can be used as a port. 3. when csie0=0, coi becomes 0. remark : dont care sbi mode 6543210 7 symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output 0 r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 1 csim00 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit si0/sb0/p25 pin function so0/sb1/p26 pin function sck0/p27 pin function 10 0 0 0 0 0 0 1 1 note 2 note 2 note 2 note 2 msb p25 (cmos input/output) sb0 (n-ch open-drain input/output) sb1 (n-ch open-drain input/output) p26 (cmos input/output) wup 0 1 wake-up function control interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after bus release (when cmdd=reld=1) matches the slave address register data in sbi mode r/w 11 3-wire serial i/o mode (15.4.2, ?-wire serial i/o mode operation.? 2-wire serial i/o mode (see section 15.4.4, ?-wire serial i/o mode operation.? coi 0 slave address comparison result flag note3 slave address register not equal to serial i/o shift register 0 data slave address register equal to serial i/o shift register 0 data r 1 csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 sck0 (cmos input/output)
264 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (b) serial bus interface control register (sbic) sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic to 00h. the shaded area is used in the sbi mode. note bits 2, 3, and 6 (reld, cmdd and ackd) are read-only bits. remark bits 0, 1, and 4 (relt, cmdt, and ackt) are 0 when read after data setting. (continued) 6543210 7 symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt used for bus release signal output. when relt = 1, so iatch is set to (1). after so latch setting, automatically cleared to (0). also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w note address after reset r/w cmdt used for command signal output. when cmdt = 1, so iatch is cleared to (0). after so latch clearance, automatically cleared to (0). also cleared to 0 when csie0 = 0. r/w r reld bus release detection set conditions (reld = 1) clear conditions (reld = 0) ?when bus release signal (rel) is detected ?when transfer start instruction is executed ?if sio0 and sva values do not match in address reception ?when csie0 = 0 ?when reset input is applied r cmdd command detection clear conditions (cmdd = 0) ?when transfer start instruction is executed ?when bus release signal (rel) is detected ?when csie0 = 0 ?when reset input is applied set conditions (cmdd = 1) ?when command signal (cmd) is detected acknowledge signal is output in synchronization with the falling edge clock of sck0 just after execution of the instruction to be set to (1) and, after acknowledge signal output, automatically cleared to (0). used as acke=0. also cleared to (0) upon start of serial interface transfer or when csie0 = 0. r/w acke acknowledge signal output control 0 acknowledge signal automatic output disable (output with ackt enable) acknowledge signal is output in synchronization with the 9th clock falling edge of sck0 (automatically output when acke = 1). before completion of transfer acknowledge signal is output in synchronization with falling edge clock of sck0 just after execution of the instruction to be set to 1 (automatically output when acke = 1). however, not automatically cleared to 0 after acknowledge signal output. after completion of transfer 1 r/w ackt
265 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 note busy mode can be cleared by start of serial interface transfer or reception of address signal. however, bsye flag is not cleared to 0. r ackd acknowledge detection clear conditions (ackd = 0) ? sck0 fall immediately after the busy mode is released during the transfer start instruction execution. ? when csie0 = 0 ? when reset input is applied set conditions (ackd = 1) ? when acknowledge signal (ack) is detected at the rising edge of sck0 clock after completion of transfer bsye synchronizing busy signal output control 0 disables busy signal which is output in synchronization with the falling edge of sck0 clock just after execution of the instruction to be cleared to (0). r/w note 1 outputs busy signal at the falling edge of sck0 clock following the acknowledge signal. *
266 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (c) interrupt timing specify register (sint) sint is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sint to 00h. the shaded area is used in the sbi mode. notes 1. bit 6 (cld) is a read-only bit. 2. when using wake-up function in the sbi mode, set sic to 0. 3. when csie0 = 0, cld becomes 0. caution be sure to set bit 0 to bit 3 to 0. remark sva : slave address register 6543210 7 symbol sint 0 cld sic svam 0 0 0 0 ff63h 00h r/w note 1 address after reset r/w svam 0 1 sva bit to be used as slave address bits 0 to 7 bits 1 to 7 sic 0 intcsi0 interrupt factor selection note 2 csiif0 is set upon termination of serial interface channel 0 transfer csiif0 is set upon bus release detection or termination of serial interface channel 0 transfer cld 0 1 sck0 pin level note 3 low level high level r/w r/w r 1
267 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (4) various signals figures 15-20 to 15-25 show various signals and flag operations in sbi. table 15-3 lists various signals in sbi. figure 15-20. relt, cmdt, reld, and cmdd operations (master) figure 15-21. reld and cmdd operations (slave) sck0 sb0 (sb1) relt cmdt cmdd reld sio0 slave address write to sio0 (transfer start instruction) * write ffh to sio0 (transfer start instruction) sio0 sck0 sb0 (sb1) reld cmdd transfer start instruction a7 a6 a1 a0 12 789 ready a7 a6 a1 a0 ack slave address when addresses match when addresses do not match
268 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 sck0 6 sb0 (sb1) ackt 7 8 9 d2 d1 d0 ack when set during this period ack signal is output for a period of one clock just after setting figure 15-22. ackt operation caution do not set ackt before termination of transfer.
269 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 sb0 (sb1) acke if set and cleared during this period and acke = 0 at the falling edge of sck0 ack signal is not output d2 d1 d0 sck0 sb0 (sb1) acke 1 2 789 d7 d6 d2 d1 d0 when acke = 0 at this p oint ack signal is not output sck0 sb0 (sb1) acke 1 2 789 d7 d6 d2 d1 d0 ack when acke = 1 at this p oint ack signal is output at 9th clock sck0 figure 15-23. acke operations (a) when acke = 1 upon completion of transfer (b) when set after completion of transfer (c) when acke = 0 upon completion of transfer (d) when acke = 1 period is short sb0 (sb1) acke 7 89 d1 d0 ack 6 d2 if set during this period and acke = 1 at the fallin g ed g e of the next sck0 ack signal is output for a period of one clock just after setting sck0
270 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 sck0 sb0 (sb1) ackd 789 d1 d0 ack 6 d2 transfer start instruction sio0 transfer start figure 15-24. ackd operations (a) when ack signal is output at 9th clock of sck0 (b) when ack signal is output after 9th clock of sck0 (c) clear timing when transfer start is instructed in busy figure 15-25. bsye operation sb0 (sb1) ackd ack 9 sio0 78 d1 6 d2 d0 transfer start instruction transfer start sck0 sck0 sb0 (sb1) ackd ack 9 transfer start instruction sio0 78 d1 6 d2 d0 d6 d7 busy sck0 sb0 (sb1) bsye 7 89 ack 6 when bsye = 1 at this point busy if reset during this period and bsye = 0 at the falling edge of sck0 d2 d1 d0
271 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 sck0 d0 ready sb0 (sb1) d0 ready sb0 (sb1) ack busy busy ack 9 sck0 "h" sb0 (sb1) "h" sb0 (sb1) sck0 table 15-3. various signals in sbi mode (1/2) timing chart definition signal name output device output condition effects on flag meaning of signal cmd signal is output to indicate that transmit data is an address. i) transmit data is an address after rel signal output. ii) rel signal is not output and trans- mit data is an command. low-level signal to be output to sb0 (sb1) during one-clock period of sck0 after completion of serial reception [synchronous busy signal] low-level signal to be output to sb0 (sb1) following acknowledge signal 1 bsye = 0 2 execution of instruction for data write to sio0 (transfer start instruction) 3 address signal reception master/ slave sb0 (sb1) rising edge when sck0 = 1 master bus release signal (rel) ? relt set ? reld set ? cmdd clear ? cmdd set ? cmdt set master command signal (cmd) sb0 (sb1) falling edge when sck0 = 1 acknowledge signal (ack) 1 acke = 1 2 ackt set ? ackd set completion of reception slave busy signal (busy) ? bsye = 1 serial receive disable because of process- ing serial receive enable slave ready signal (ready) high-level signal to be output to sb0 (sb1) before serial transfer start and after completion of serial transfer [synchronous busy output]
272 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 timing chart definition signal name output device output condition effects on flag meaning of signal synchronous clock to output address/command/ data, ack signal, synchro- nous busy signal, etc. address/command/data are transferred with the first eight synchronous clocks. 8-bit data to be transferred in synchronization with sck0 after output of only cmd signal without rel signal output master numeric values to be processed with slave or master device serial clock (sck0) timing of signal output to serial data bus address value of slave device on the serial bus address (a7 to a0) 8-bit data to be transferred in synchronization with sck0 after output of rel and cmd signals master commands (c7 to c0) instructions and messages to the slave device master/ slave data (d7 to d0) 8-bit data to be transferred in synchronization with sck0 without output of rel and cmd signals table 15-3. various signals in sbi mode (2/2) when csie0 = 1, execution of instruction for data write to sio0 (serial transfer start instruction) note 2 notes 1. when wup = 0, csiif0 is set at the rising edge of the 9th clock of sck0. when wup = 1, an address is received. only when the address matches the slave address register (sva) value, csiif0 is set. 2. in busy state, transfer starts after the ready state is set. master csiif0 set (rising edge of 9th clock of sck0) note 1 sck0 sb0 (sb1) 1278 sck0 sb0 (sb1) 1278 cmd sck0 sb0 (sb1) 1278 rel cmd sck0 sb0 (sb1) 1278910
273 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (5) pin configuration the serial clock pin (sck0) and serial data bus pin sb0 (sb1) have the following configurations. (a) sck0 ............. serial clock input/output pin 1 master ... cmos and push-pull output 2 slave ...... schmitt input (b) sb0 (sb1) ..... serial data input/output dual-function pin both master and slave devices have an n-ch open drain output and a schmitt input. because the serial data bus line has an n-ch open-drain output, an external pull-up resistor is necessary. figure 15-26. pin configuration caution because the n-ch open-drain must be turned off at time of data reception, write ffh to sio0 in advance. the n-ch open-drain can be turned off at any time of transfer. however, when the wake-up function specify bit (wup) = 1, the n-ch transistor is always turned off. thus, it is not necessary to write ffh to sio0. si0 so0 si0 so0 (clock input) clock output master device clock input (clock output) serial clock sck0 sck0 r l serial data bus sb0 (sb1) sb0 (sb1) n-ch open drain n-ch open drain slave device
274 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (6) address match detection method in the sbi mode, a particular slave device is selected by address communication from the master device and communication is started. address match detection is executed by hardware. with the slave address register (sva), csiif0 is set in the wake-up state (wup = 1) only when the address transmitted from the master device matches the value set to sva. cautions 1. slave selection/non-selection is detected by matching of the slave address received after bus release (reld = 1). for this match detection, match interrupt (intcsi0) of the address to be generated with wup = 1 is normally used. thus, execute selection/non-selection detection by slave address when wup = 1. 2. when detecting selection/non-selection without the use of interrupt with wup = 0, do so by means of transmission/reception of the command preset by program instead of using the address match detection method. (7) error detection in the sbi mode, the serial bus sb0 (sb1) status being transmitted is fetched into the destination device, that is, the serial i/o shift register 0 (sio0). thus, transmit errors can be detected in the following way. (a) method of comparing sio0 data before transmission to that after transmission in this case, if two data differ from each other, a transmit error is judged to have occurred. (b) method of using the slave address register (sva) transmit data is set to both sio0 and sva and is transmitted. after termination of transmission, coi bit (match signal coming from the address comparator) of the serial operating mode register 0 (csim0) is tested. if 1, normal transmission is judged to have been carried out. if 0, a transmit error is judged to have occurred. (8) communication operation in the sbi mode, the master device selects normally one slave device as communication target from among two or more devices by outputting an address to the serial bus. after the communication target device has been determined, commands and data are transmitted/received and serial communication is realized between the master and slave devices. figures 15-27 to 15-30 show data communication timing charts. shift operation of the shift register is carried out at the falling edge of serial clock (sck0). transmit data is latched into the so0 latch and is output with msb set as the first bit from the sb0/p25 or sb1/p26 pin. receive data input to the sb0 (or sb1) pin at the rising edge of sck0 is latched into the shift register.
275 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 figure 15-27. address transmission from master device to slave device (wup = 1) 1 2 3 4 5 6 7 8 9 sck0 pin a7 a6 a5 a4 a3 a2 a1 a0 ack busy sb0 (sb1) pin program processing serial transmission intcsi0 generation ackd set sck0 stop hardware operation wup ? 0 ackt set program processing cmdd set intcsi0 generation ack output hardware operation cmdt set relt set cmdt set write to sio0 interrupt servicing (preparation for the next serial transfer) master device processing (transmitter) transfer line slave device processing (receiver) cmdd clear cmdd set reld set serial reception busy output ready (when sva = sio0) address busy clear busy clear
276 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 figure 15-28. command transmission from master device to slave device 1 2 3 4 5 6 7 8 9 sck0 pin c7 c6 c5 c4 c3 c2 c1 c0 ack busy sb0 (sb1) pin program processing serial transmission intcsi0 generation ackd set sck0 stop hardware operation ackt set program processing intcsi0 generation ack output hardware operation cmdt set write to sio0 interrupt servicing (preparation for the next serial transfer) master device processing (transmitter) transfer line slave device processing (receiver) cmdd set serial reception busy output ready command busy clear busy clear sio0 read command analysis
277 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 figure 15-29. data transmission from master device to slave device 1 2 3 4 5 6 7 8 9 sck0 pin d7 d6 d5 d4 d3 d2 d1 d0 ack busy sb0 (sb1) pin program processing serial transmission intcsi0 generation ackd set sck0 stop hardware operation ackt set program processing intcsi0 generation ack output hardware operation write to sio0 interrupt servicing (preparation for the next serial transfer) master device processing (transmitter) transfer line slave device processing (receiver) serial reception busy output ready data busy clear busy clear sio0 read
278 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 figure 15-30. data transmission from slave device to master device 1 2 3 4 5 6 7 8 9 sck0 pin d7 d6 d5 d4 d3 d2 d1 d0 ack busy sb0 (sb1) pin program processing serial reception intcsi0 generation ack output serial reception hardware operation program processing intcsi0 generation ackd set hardware operation ffh write to sio0 master device processing (receiver) transfer line slave device processing (transmitter) serial transmission busy output ready data busy clear write to sio0 sck0 stop busy clear 12 ready busy d7 d6 ackt set sio0 read receive data processing ffh write to sio0 write to sio0
279 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (9) transfer start serial transfer is started by setting transfer data to the serial i/o shift register 0 (sio0) when the following two conditions are satisfied. ? serial interface channel 0 operation control bit (csie0) = 1 ? internal serial clock is stopped or sck0 is at high level after 8-bit serial transfer. cautions 1. if csie0 is set to 1 after data write to sio0, transfer does not start. 2. because the n-ch transistor must be turned off for data reception, write ffh to sio0 in advance. however, when the make-up function specify bit (wup) = 1, the n-ch transistor is always turned off. thus, it is not necessary to write ffh to sio0. 3. if data is written to sio0 when the slave is busy, the data is not lost. when the busy state is cleared and sb0 (or sb1) input is set to the high level (ready) state, transfer starts. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set.
280 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (10) sbi mode precautions (a) slave selection/non-selection is detected by match detection of the slave address received after bus release (reld = 1). for this match detection, match interrupt (intcsi0) of the address to be generated with wup = 1 is normally used. thus, execute selection/non-selection detection by slave address when wup = 1. (b) when detecting selection/non-selection without the use of interrupt with wup = 0, do so by means of transmission/reception of the command preset by program instead of using the address match detection method. (c) if wup is set to 1 during busy signal output, busy is not cleared. in sbi, the busy signal continues to be output after busy clear instruction generation to the falling edge of the next serial clock (sck0). before setting wup to 1, be sure to clear busy and then check that the sb0 (sb1) has become high- level. (d) for pins which are to be used for data input/output, be sure to carry out the following settings before serial transfer of the 1st byte after reset input. <1> set the p25 and p26 output latches to 1. <2> set bit 0 (relt) of the serial bus interface control register to 1. <3> reset the p25 and p26 output latches from 1 to 0. (e) when device is in the master mode, follow the procedure below to judge whether slave device is in the busy state or not. <1> detect acknowledge signal (ack) or interrupt request signal generation. <2> set the port mode register pm25 (or pm26) of the sb0/p25 (or sb1/p26) pin into the input mode. <3> read out the pin state (when the pin level is high, the ready state is set). after the detection of the ready state, set the port mode register to 0 and return to the output mode.
281 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 15.4.4 2-wire serial i/o mode operation the 2-wire serial i/o mode can cope with any communication format by program. communication is basically carried out with two lines of serial clock (sck0) and serial data input/output (sb0 or sb1). figure 15-31. serial bus configuration example using 2-wire serial i/o mode master sck0 slave sb0 (sb1) sck0 sb0 (sb1) v dd v dd
282 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (1) register setting the 2-wire serial i/o mode is set with the serial operating mode register 0 (csim0), the serial bus interface control register (sbic), and the interrupt timing specify register (sint). (a) serial operating mode register 0 (csim0) csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. the shaded area is used in the 2-wire serial i/o mode. notes 1. bit 6 (coi) is a read-only bit. 2. can be used freely as port function. 3. be sure to set wup to 0 when the 2-wire serial i/o mode. 4. when csie0=0, coi becomes 0. remark : dont care * 6543210 7 symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 csim00 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit sio/sb0/p25 pin function so0/sb1/p26 pin function sck0/p27 pin function 10 wup 0 1 wake-up function control interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after bus release (when cmdd=reld=1) matches the slave address register data in sbi mode r/w 2-wire serial l/o mode 0 1 11 0 0 0 0 0 0 1 1 note 2 note 2 note 2 note 2 msb p25 (cmos input/output sb0 (n-ch open-drain input/output) sb1 (n-ch open-drain input/output) p26 (cmos input/output) 3-wire serial i/o mode (see section 15.4.2, ?-wire serial i/o mode operation sbi mode (see section 15.4.3, ?bi mode operation note 3 coi 0 slave address comparison result flag note4 slave address register not equal to serial i/o shift register 0 data slave address register equal to serial i/o shift register 0 data r 1 csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 sck0 (n-ch open-drain input/output)
283 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (b) serial bus interface control register (sbic) sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic to 00h. the shaded area is used in the 2-wire serial i/o mode. 6543210 7 symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt when relt = 1, so iatch is set to 1. after so iatch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w address after reset r/w cmdt when cmdt = 1, so iatch is cleared to 0. after so latch clearance, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w
284 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (c) interrupt timing specify register (sint) sint is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sint to 00h. the shaded area is used in the 2-wire serial i/o mode. notes 1. bit 6 (cld) is a read-only bit. 2. when csie0 = 0, cld becomes 0. caution be sure to set bit 0 to bit 3 to 0. 6543210 7 symbol sint 0 cld sic 0 0 0 0 ff63h 00h r/w note 1 address after reset r/w sic 0 intcsi0 interrupt factor selection csiif0 is set upon termination of serial interface channel 0 transfer csiif0 is set upon bus release detection or termination of serial interface channel 0 transfer cld 0 1 sck0 pin level note 2 low level high level r/w r 1 svam *
285 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (2) communication operation the 2-wire serial i/o mode is used for data transmission/reception in 8-bit units. data transmission/reception is carried out bit-wise in synchronization with the serial clock. shift operation of the serial i/o shift register 0 (sio0) is carried out in synchronization with the falling edge of the serial clock (sck0). the transmit data is held in the so0 latch and is output from the sb0/p25 (or sb1/ p26) pin on an msb-first basis. the receive data input from the sb0 (or sb1) pin is latched into the shift register at the rising edge of sck0. upon termination of 8-bit transfer, the shift register operation stops automatically and the interrupt request flag (csiif0) is set. figure 15-32. 2-wire serial i/o mode timings the sb0 (or sb1) pin specified for the serial data bus is an n-ch open-drain input/output and thus it must be externally connected to a pull-up resistor. because it is necessary to turn off the n-ch transistor for data reception, write ffh to sio0 in advance. the sb0 (or sb1) pin generates the so0 latch status and thus the sb0 (or sb1) pin output status can be manipulated by setting the relt and cmdt bits. however, do not carry out this manipulation during serial transfer. control the sck0 pin output level in the output mode (internal system clock mode) by manipulating the p27 output latch (refer to 15.4.5 sck0/p27 pin output manipulation ). 123 4 5 6 7 8 sck0 d7 d6 d5 d4 d3 d2 d1 d0 sb0 (sb1) csiif0 transfer start at the fallin g ed g e of sck0 end of transfer
286 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 (3) other signals figure 15-33 shows relt and cmdt operations. figure 15-33. relt and cmdt operations (4) transfer start serial transfer is started by setting transfer data to the serial i/o shift register 0 (sio0) when the following two conditions are satisfied. ? serial interface channel 0 operation control bit (csie0) = 1 ? internal serial clock is stopped or sck0 is at high level after 8-bit serial transfer. cautions 1. if csie0 is set to 1 after data write to sio0, transfer does not start. 2. because the n-ch transistor must be turned off for data reception, write ffh to sio0 in advance. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. (5) error detection in the 2-wire serial i/o mode, the serial bus sb0 (sb1) status being transmitted is fetched into the destination device, that is, sio0. thus, transmit error can be detected in the following way. (a) method of comparing sio0 data before transmission to that after transmission in this case, if two data differ from each other, a transmit error is judged to have occurred. (b) method of using the slave address register (sva) transmit data is set to both sio0 and sva and is transmitted. after termination of transmission, coi bit (match signal coming from the address comparator) of the serial operating mode register 0 (csim0) is tested. if 1, normal transmission is judged to have been carried out. if 0, a transmit error is judged to have occurred. relt cmdt so0 latch
287 chapter 15 serial interface channel 0 ( m pd78064 subseries) users manual u10105ej4v1um00 15.4.5 sck0/p27 pin output manipulation because the sck0/p27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. p27 output latch manipulation enables any number of sck0 to be set by software. (si0/sb0 and so0/sb1 pin to be controlled with the relt and cmdt bits of sbic.) sck0/p27 pin output manipulating procedure is described below. 1 set the serial operating mode register 0 (csim0) (sck0 pin is set in the output mode and serial operation is enabled). while serial transfer is suspended, sck0 is set to 1. 2 manipulate the content of the p27 output latch by executing the bit manipulation instruction. figure 15-34. sck0/p27 pin configuration to internal circuit sck0/p27 p27 output latch when csie0 = 1 and csim01 and csim00 are 1 and 0 , or 1 and 1. sck0 (1 when transfer stops) from serial clock control circuit set by bit manipulation instruction *
288 users manual u10105ej4v1um00 [memo]
289 users manual u10105ej4v1um00 chapter 16 serial interface channel 0 ( m pd78064y subseries) the m pd78064y subseries incorporates two channels of serial interfaces. differences between channels 0 and 2 are as follows (refer to chapter 17 serial interface channel 2 for details of the serial interface channel 2). table 16-1. differences between channels 0 and 2 * serial transfer mode channel 0 f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xx /2 8 , external clock, to2 output msb/lsb switchable as the start bit serial transfer end interrupt request flag (csiif0) clock selection transfer method transfer end flag i 2 c bus (inter ic bus) 2-wire serial i/o uart (asynchronous serial interface) use possible none 3-wire serial i/o channel 2 external clock, baud rate generator output msb/lsb switchable as the start bit serial transfer end interrupt request flag (srif) none use possible
290 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 16.1 serial interface channel 0 functions serial interface channel 0 employs the following four modes. ? operation stop mode ? 3-wire serial i/o mode ? 2-wire serial i/o mode ?i 2 c (inter ic) bus mode (1) operation stop mode this mode is used when serial transfer is not carried out. power consumption can be reduced. (2) 3-wire serial i/o mode (msb-/lsb-first selectable) this mode is used for 8-bit data transfer using three lines, one each for serial clock (sck0), serial output (so0) and serial input (si0). this mode enables simultaneous transmission/reception and therefore reduces the data transfer processing time. the start bit of transferred 8-bit data is switchable between msb and lsb, so that devices can be connected regardless of their start bit recognition. this mode should be used when connecting with peripheral i/o devices or display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75x, 78k, and 17k series. (3) 2-wire serial i/o mode (msb-first) this mode is used for 8-bit data transfer using two lines of serial clock (sck0) and serial data bus (sb0 or sb1). this mode enables to cope with any one of the possible data transfer formats by controlling the sck0 level and the sb0 or sb1 output level. thus, the handshake line previously necessary for connection of two or more devices can be removed, resulting in the increased number of available input/output ports.
291 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (4) i 2 c (inter ic) bus mode (msb-first) this mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (scl) and serial data bus (sda0 or sda1). this mode is in compliance with the i 2 c bus format. in this mode, the transmitter outputs three kinds of data onto the serial data bus: start condition, data, and stop condition, to be actually sent or received. the receiver automatically distinguishes the received data into start condition, data, or stop condition, by hardware. figure 16-1. serial bus configuration example using i 2 c bus master cpu scl sda0 (sda1) scl sda0 (sda1) slave cpu1 slave cpu2 slave cpun v dd v dd scl sda0 (sda1) scl sda0 (sda1)
292 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 16.2 serial interface channel 0 configuration serial interface channel 0 consists of the following hardware. table 16-2. serial interface channel 0 configuration item configuration serial i/o shift register 0 (sio0) slave address register (sva) timer clock select register 3 (tcl3) serial operating mode register 0 (csim0) control register serial bus interface control register (sbic) interrupt timing specify register (sint) port mode register 2 (pm2) register
293 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 csie0 coi wup csim 04 csim 03 csim 02 csim 01 csim 00 serial operating mode register 0 control circuit output control selector si0/sb0/ sda0/p25 pm25 output control so0/sb1/ sda1/p26 pm26 output control sck0/ scl/p27 pm27 p25 output latch p26 output latch cld p27 output latch internal bus bsye ackd acke ackt cmdd reld cmdt relt internal bus stop condition/ start condition/ acknowledge detector serial clock counter serial clock control circuit clr d set q match acknowledge output circuit interrupt request signal generator ackd cmdd reld wup selector selector f xx /2-f xx /2 8 intcsi0 csim01 csim00 to2 1/16 divider csim01 csim00 slave address register (sva) serial bus interface control register cld sic svam clc wrel wat1 wat0 interrupt timing specify register 2 serial i/o shift register 0 (sio0) 4 tcl33 tcl32 tcl31 tcl30 timer clock select register 3 selector bsye svam figure 16-2. serial interface channel 0 block diagram remark output control performs selection between cmos output and n-ch open drain output.
294 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (1) serial i/o shift register 0 (sio0) this is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. sio0 is set with an 8-bit memory manipulation instruction. when bit 7 (csie0) of serial operating mode register 0 (csim0) is 1, writing data to sio0 starts serial operation. in transmission, data written to sio0 is output to the serial output (so0) or serial data bus (sb0/sb1). in reception, data is read from the serial input (si0) or sb0/sb1 to sio0. note that, if a bus is driven in the i 2 c bus mode or 2-wire serial i/o mode, the bus pin must serve for both input and output. therefore, the transmission n-ch transistor of the device which will start reception of data must be turned off beforehand. consequently, write ffh to sio0 in advance. in the i 2 c bus mode, set sio0 to ffh with bit 7 (bsye) of the serial bus interface control register (sbic) set to 0. reset input makes sio0 undefined. (2) slave address register (sva) this is an 8-bit register to set the slave address value for connection of a slave device to the serial bus. sva is set with an 8-bit memory manipulation instruction. the master device outputs a slave address for selection of a particular slave device to the connected slave device. these two data (the slave address output from the master device and the sva value) are compared with an address comparator. if they match, the slave device has been selected. in that case, bit 6 (coi) of serial operating mode register 0 (csim0) becomes 1. address comparison can also be executed on the data of lsb-masked high-order 7 bits with bit 4 (svam) of the interrupt timing specify register (sint). if no matching is detected in address reception, bit 2 (reld) of the serial bus interface control register (sbic) is cleared to 0. when bit 5 (wup) of csim0 is 1, the interrupt request signal (intcsi0) is generated only if the matching is detected. this interrupt request enables to recognize the generation of the communication request from the master device. further, when sva transmits data as master or slave device in the the i 2 c bus mode or 2-wire serial i/o mode, errors are detected if any. reset input makes sva undefined. (3) so0 latch this latch holds si0/sb0/sda0/p25 and so0/sb1/sda1/p26 pin levels. it can be directly controlled by software. (4) serial clock counter this counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received. (5) serial clock control circuit this circuit controls serial clock supply to the serial i/o shift register 0 (sio0). when the internal system clock is used, the circuit also controls clock output to the sck0/scl/p27 pin.
295 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (6) interrupt request signal generator this circuit controls interrupt request signal generation. it generates interrupt request signals according to the settings of interrupt timing specification register (sint) bits 0 and 1 (wat0, wat1) and serial operation mode register 0 (csim0) bit 5 (wup), as shown in table 16-3. (7) acknowledge output circuit and stop condition/start condition/acknowledge detector these two circuits output and detect various control signals in the i 2 c mode. these do not operate in the 3-wire serial i/o mode and 2-wire serial i/o mode. table 16-3. serial interface channel 0 interrupt request signal generation serial transfer mode bsye wup wat1 wat0 acke description 3-wire or 2-wire serial i/o mode 0 0 0 0 0 an interrupt request signal is generated each time 8 serial clocks are counted. other than above setting prohibited i 2 c bus mode (transmit) 0 0 1 0 0 an interrupt request signal is generated each time 8 serial clocks are counted (8-clock wait). normally, during transmission the settings wat21, wat0=1, 0, are not used. they are used only when wanting to coordinate receive time and processing systematically using software. ack information is generated by the receiving side, thus acke should be set to 0 (disable). 1 1 0 an interrupt request signal is generated each time 9 serial clocks are counted (9-clock wait). ack information is generated by the receiving side, thus acke should be set to 0 (disable). other than above setting prohibited i 2 c bus mode (receive) 1 0 1 0 0 an interrupt request signal is generated each time 8 serial clocks are counted (8-clock wait). ack information is output by manipulating ackt by software after an interrupt is generated. 1 1 0/1 an interrupt request signal is generated each time 9 serial clocks are counted (9-clock wait). to automatically generate ack information, preset acke to 1 before transfer start. however, in the case of the master, set acke to 0 (disable) before receiving the last data. 1 1 1 1 1 after address is received, if the values of the serial i/o shift register 0 (si00) and the slave address register (sva) match, an interrupt request signal is generated. to automatically generate ack information, preset acke to 1 (enable) before transfer start. other than above s etting prohibited remark bsye: bit 7 of serial bus interface control register (sbic) acke: bit 5 of serial bus interface control register (sbic)
296 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 16.3 serial interface channel 0 control registers the following four types of registers are used to control serial interface channel 0. ? timer clock select register 3 (tcl3) ? serial operating mode register 0 (csim0) ? serial bus interface control register (sbic) ? interrupt timing specify register (sint) (1) timer clock select register 3 (tcl3) this register sets the serial clock of serial interface channel 0. tcl3 is set with an 8-bit memory manipulation instruction. reset input sets tcl3 to 88h.
297 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 figure 16-3. timer clock select register 3 format cautions 1. set bit 4 to bit 6 to 0, and bit 7 to 1. 2. when rewriting tcl3 to other data, stop the serial transfer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs : oscillation mode selection register bit 0 4. figures in parentheses apply to operation with f x = 5.0 mhz. serial interface channel 0 serial clock selection tcl33 tcl32 tcl31 tcl30 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 f xx /2 9 f xx /2 10 f xx /2 11 f xx /2 12 mcs = 1 setting prohibited f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.77 khz) f x /2 10 (4.88 khz) f x /2 11 (2.44 khz) f x /2 12 (1.22 khz) mcs = 1 setting prohibited f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) other than above setting prohibited 6543210 7 symbol tcl3 1 0 0 0 tcl33 tcl32 tcl31 tcl30 ff43h 88h r/w address after reset r/w mcs = 0 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.77 khz) f x /2 10 (4.88 khz) f x /2 11 (2.44 khz) f x /2 12 (1.22 khz) f x /2 13 (0.61 khz) f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 mcs = 0 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) serial clock in i 2 c bus mode serial clock in 2-wire or 3-wire serial i/o mode
298 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (2) serial operating mode register 0 (csim0) this register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. figure 16-4. serial operating mode register 0 format notes 1. bit 6 (coi) is a read-only bit. 2. i 2 c bus mode, the clock frequency becomes 1/16 of that output from to2. 3. can be used as p25 (cmos input/output) when used only for transmission. 4. can be used freely as port function. 5. when csie0 = 0, coi becomes 0. remark : dont care 6543210 7 symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0/scl pin from off-chip 8-bit timer register 2 (tm2) output 0 r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 csim00 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit si0/sb0/sda0/ p25 pin function so0/sb1/sda1/ p26 pin function sck0/scl/p27 pin function 1 msb lsb 1 0001 note3 3-wire serial l/o mode si0 (input) so0 (cmos output) sck0 (cmos input/output) note3 2-wire serial l/o mode or i 2 c bus mode 0 sck0/scl (n-ch open-drain input/output) 1 11 0 0 0 0 0 0 1 1 note4 note4 note4 note4 msb p25 (cmos input/output) sb0/sda0 (n-ch open-drain input/output) sb1/sda1 (n-ch open-drain input/output) p26 (cmos input/output) note3 wup 0 1 wake-up function control interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after detecting start condition (when cmdd = 1) matches the slave address register data in i 2 c bus mode r/w coi 0 1 slave address comparison result flag note5 slave address register not equal to serial i/o shift register 0 data slave address register equal to serial i/o shift register 0 data r csie0 0 1 serial interface channel 0 operation control operation stopped operation enabled r/w note2
299 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (3) serial bus interface control register (sbic) this register sets serial bus interface operation and displays statuses. sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic to 00h. figure 16-5. serial bus interface control register format (1/2) note bits 2, 3, and 6 (reld, cmdd and ackd) are read-only bits. 6543210 7 symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt used for stop condition signal output. when relt = 1, so iatch is set to 1. after so latch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w note address after reset r/w cmdt used for start condition signal output. when cmdt = 1, so iatch is cleared to (0). after so latch clearance, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w r reld stop condition detection set conditions (reld =1) clear conditions (reld = 0) when stop condition signal is detected ?when transfer start instruction is executed ?if sio0 and sva values do not match in address reception ?when csie0 = 0 ?when reset input is applied r cmdd start condition detection clear conditions (cmdd = 0) ?when transfer start instruction is executed ?when stop condition signal is detected ?when csie0 = 0 ?when reset input is applied set conditions (cmdd = 1) ?when start condition signal is detected ackt used to generate the ack signal by software when 8-clock wait mode is selected. keeps sda0 (sda1) low from set instruction (ackt=1) execution to the next falling edge of scl. also cleared to 0 upon start of serial interface transfer or when csie0 = 0. r/w
300 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 figure 16-5. serial bus interface control register format (2/2) notes 1. setting should be performed before transfer. 2. if 8-clock wait mode is selected, the acknowledge signal at reception time must be output using ackt. 3. the busy mode can be canceled by start of serial interface transfer or reception of address signal. however, the bsye flag is not cleared to 0. 4. when using the wake-up function, be sure to set bsye to 1. acke acknowledge signal output control 0 disables acknowledge signal automatic output. (however, output with ackt is enabled) used for reception when 8-clock wait mode is selected or for transmission. note2 enables acknowledge signal automatic output. outputs acknowledge signal in synchronization with the falling edge of the 9th scl clock cycle (automatically output when acke = 1). however, not automatically cleared to 0 after acknowledge signal output. used in reception with 9-clock wait mode selected. 1 r/w r ackd acknowledge detection clear conditions (ackd = 0) while executing the transfer start instruction ?when csie0 = 0 ?when reset input is applied set conditions (ackd = 1) ?when acknowledge signal (ack) is detected at the rising edge of scl clock after completion of transfer bsye control of n-ch open-drain output for transmission in i 2 c bus mode 0 output enabled (transmission) r/w note3 1 note4 output disabled (reception) note1
301 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (4) interrupt timing specify register (sint) this register sets the bus release interrupt and address mask functions and displays the sck0/scl pin level status. sint is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sint to 00h. figure 16-6. interrupt timing specify register format (1/2) notes 1. bit 6 (cld) is a read-only bit. 2. when not using the i 2 c mode, set clc to 0. used in i 2 c bus mode. make scl pin enter high-impedance state unless serial transfer is being performed. (except for clock line which is kept high) used to enable master device to generate start condition and stop condition signals. 6543210 7 symbol sint 0 cld sic svam clc wrel wat1 wat0 ff63h 00h r/w note 1 address after reset r/w wrel 0 wait state has been cancelled. cancels wait state. automatically cleared to 0 when the state is cancelled. (used to cancel wait state by means of wat0 and wat1.) clc 0 1 clock level control note2 used in i 2 c bus mode. make output level of scl pin low unless serial transfer is being performed. r/w 1 wait sate cancellation control r/w wat1 0 1 wait and interrupt control generates interrupt service request at rising edge of 8th sck0 clock cycle. (keeping clock output in high impedance) r/w wat0 0 0 used in i 2 c bus mode. (8-clock wait) generates interrupt service request at rising edge of 8th sck0 clock cycle. (in the case of master device, makes scl output low to enter wait state after 8 clock pulses are output. in the case of slave device, makes scl output low to request wait state after 8 clock pulses are input.) 1 1 used in i 2 c bus mode. (9-clock wait) generates interrupt service request at rising edge of 9th sck0 clock cycle. (in the case of master device, makes scl output low to enter wait state after 9 clock pulses are output. in the case of slave device, makes scl output low to request wait state after 9 clock pulses are input.) 0 setting prohibited 1
302 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 figure 16-6. interrupt timing specify register format (2/2) notes 1. when using wake-up function in the i 2 c mode, set sic to 1. 2. when csie0 = 0, cld becomes 0. remark sva : slave address register svam 0 1 sva bit to be used as slave address bits 0 to 7 bits 1 to 7 sic 0 intcsi0 interrupt cause selection note1 csiif0 is set to 1 upon termination of serial interface channel 0 transfer csiif0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer cld 0 1 sck0/scl pin level note2 low level high level r/w r/w r 1
303 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 16.4 serial interface channel 0 operations the following four operating modes are available to the serial interface channel 0. ? operation stop mode ? 3-wire serial i/o mode ? 2-wire serial i/o mode ?i 2 c (inter ic) bus mode 16.4.1 operation stop mode serial transfer is not carried out in the operation stop mode. thus, power consumption can be reduced. the serial i/o shift register 0 (sio0) does not carry out shift operation either and thus it can be used as ordinary 8-bit register. in the operation stop mode, the p25/si0/sb0/sda0, p26/so0/sb1/sda1 and p27/sck0/scl pins can be used as general input/output ports. (1) register setting the operation stop mode is set with the serial operating mode register 0 (csim0). csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. the shaded area is used in the operation stop mode. 6543210 7 symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 ff60h 00h r/w address after reset r/w csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1
304 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 16.4.2 3-wire serial i/o mode operation the 3-wire serial i/o mode is valid for connection of peripheral i/o units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75x, 78k, and 17k series. communication is carried out with three lines of serial clock (sck0), serial output (so0), and serial input (si0). (1) register setting the 3-wire serial i/o mode is set with the serial operating mode register 0 (csim0) and serial bus interface control register (sbic). (a) serial operating mode register 0 (csim0) csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. the shaded area is used in the 3-wire serial i/o mode. notes 1. bit 6 (coi) is a read-only bit. 2. can be used as p25 (cmos input/output) when used only for transmission. 3. be sure to set wup to 0 when the 3-wire serial i/o mode is selected. remark : dont care 6543210 7 symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output 0 2-wire serial i/o mode (see section 16.4.3, ?-wire serial i/o mode operation?) r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 csim00 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit sio/sb0/sda0 /p25 pin function so0/sb1/sda1 /p26 pin function sck0/scl/p27 pin function 11 wup 0 1 wake-up function control interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after detecting start condition (when cmdd=1) matches the slave address register data in i 2 c bus mode r/w 1 msb lsb 1 0001 note 2 3-wire serial l/o mode si0 (input) so0 (cmos output) sck0 (cmos input/output) i 2 c bus mode (see section 16.4.4, ? 2 c bus mode operation?) note 2 note 3 note 2 csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 or
305 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (b) serial bus interface control register (sbic) sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic to 00h. the shaded area is used in the 3-wire serial i/o mode. 6543210 7 symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt when relt = 1, so iatch is set to 1. after so iatch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w address after reset r/w cmdt when cmdt = 1, so iatch is cleared to 0. after so latch clearance, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w
306 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (2) communication operation the 3-wire serial i/o mode is used for data transmission/reception in 8-bit units. bit-wise data transmission/ reception is carried out in synchronization with the serial clock. shift operation of the serial i/o shift register 0 (sio0) is carried out at the falling edge of the serial clock (sck0). the transmitted data is held in the so0 latch and is output from the so0 pin. the received data input to the si0 pin is latched in sio0 at the rising edge of sck0. upon termination of 8-bit transfer, sio0 operation stops automatically and the interrupt request flag (csiif0) is set. figure 16-7. 3-wire serial i/o mode timings the so0 pin is a cmos output pin and outputs current so0 latch statuses. thus, the so0 pin output status can be manipulated by setting the relt and cmdt bits. however, do not carry out this manipulation during serial transfer. control the sck0 pin output level in the output mode (internal system clock mode) by manipulating the p27 output latch (refer to 16.4.6 sck0/scl/p27 pin output manipulation ). (3) other signals figure 16-8 shows relt and cmdt operations. figure 16-8. relt and cmdt operations si0 sck0 12345678 di7 di6 di5 di4 di3 di2 di1 di0 so0 do7 do6 do5 do4 do3 do2 do1 do0 csiif0 transfer start at the falling edge of sck0 end of transfer relt cmdt so0 latch
307 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (4) msb/lsb switching as the start bit the 3-wire serial i/o mode enables to select transfer to start from msb or lsb. figure 16-9 shows the configuration of the serial i/o shift register 0 (sio0) and internal bus. as shown in the figure, msb/lsb can be read/written in reverse form. msb/lsb switching as the start bit can be specified with bit 2 (csim02) of the serial operating mode register 0 (csim0). figure 16-9. circuit of switching in transfer bit order start bit switching is realized by switching the bit order for data write to sio0. the sio0 shift order remains unchanged. thus, switching between msb-first and lsb-first must be performed before writing data to the shift register. (5) transfer start serial transfer is started by setting transfer data to the serial i/o shift register 0 (sio0) when the following two conditions are satisfied. ? serial interface channel 0 operation control bit (csie0) = 1. ? internal serial clock is stopped or sck0 is a high level after 8-bit serial transfer. caution if csie0 is set to 1 after data write to sio0, transfer does not start. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. 7 6 internal bus 1 0 lsb-first msb-first read/write gate si0 shift register 0 (sio0) read/write gate so0 sck0 dq so0 latch
308 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 16.4.3 2-wire serial i/o mode operation the 2-wire serial i/o mode can cope with any communication format by program. communication is basically carried out with two lines of serial clock (sck0) and serial data input/output (sb0 or sb1). figure 16-10. serial bus configuration example using 2-wire serial i/o mode (1) register setting the 2-wire serial i/o mode is set with the serial operating mode register 0 (csim0), the serial bus interface control register (sbic), and the interrupt timing specify register (sint). master sck0 slave sb0 (sb1) sck0 sb0 (sb1) v dd v dd
309 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (a) serial operating mode register 0 (csim0) csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. the shaded area is used in the 2-wire serial i/o mode. notes 1. bit 6 (coi) is a read-only bit. 2. can be used freely as port function. 3. be sure to set wup to 0 when the 2-wire serial i/o mode. 4. when csie0=0, coi becomes 0. remark : dont care 6543210 7 symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 csim00 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit sio/sb0/sda0 /p25 pin function so0/sb1/sda1 /p26 pin function sck0/scl/p27 pin function wup 0 1 wake-up function control interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after detecting start condition (when cmdd=1) matches the slave address register data in i 2 c bus mode r/w 2-wire serial l/o mode or i 2 c bus mode 0 sck0/scl (n-ch open-drain input/output) 1 11 0 0 0 0 0 0 1 1 note 2 note 2 note 2 note 2 msb p25 (cmos input/output sb0/sda0 (n-ch open-drain input/output) sb1/sda1 (n-ch open-drain input/output) p26 (cmos input/output) 3-wire serial i/o mode (see section 16.4.2, ?-wire serial i/o mode operation note 3 coi 0 slave address comparison result flag note4 slave address register not equal to serial i/o shift register 0 data slave address register equal to serial i/o shift register 0 data r 1 csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1
310 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (b) serial bus interface control register (sbic) sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic to 00h. the shaded area is used in the 2-wire serial i/o mode. 6543210 7 symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt when relt = 1, so iatch is set to 1. after so iatch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w address after reset r/w cmdt when cmdt = 1, so iatch is cleared to 0. after so latch clearance, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w
311 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (c) interrupt timing specify register (sint) sint is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sint to 00h. the shaded area is used in the 2-wire serial i/o mode. notes 1. bit 6 (cld) is a read-only bit. 2. when csie0 = 0, cld becomes 0. caution be sure to set bit 0 to bit 3 to 0 when 2-wire serial i/o mode is used. 6543210 7 symbol sint 0 cld sic clc wrel wat1 wat0 ff63h 00h r/w note 1 address after reset r/w svam sic 0 intcsi0 interrupt factor selection csiif0 is set upon termination of serial interface channel 0 transfer csiif0 is set upon stop condition detection or termination of serial interface channel 0 transfer cld 0 1 sck0 pin level note 2 low level high level r/w r 1
312 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (2) communication operation the 2-wire serial i/o mode is used for data transmission/reception in 8-bit units. data transmission/reception is carried out bit-wise in synchronization with the serial clock. shift operation of the serial i/o shift register 0 (sio0) is carried out in synchronization with the falling edge of the serial clock (sck0). the transmit data is held in the so0 latch and is output from the sb0/sda0/p25 (or sb1/sda1/p26) pin on an msb-first basis. the receive data input from the sb0 (or sb1) pin is latched into the shift register at the rising edge of sck0. upon termination of 8-bit transfer, the shift register operation stops automatically and the interrupt request flag (csiif0) is set. figure 16-11. 2-wire serial i/o mode timings the sb0 (or sb1) pin specified for the serial data bus is an n-ch open-drain input/output and thus it must be externally connected to a pull-up resistor. because it is necessary to turn off the n-ch transistor for data reception, write ffh to sio0 in advance. the sb0 (or sb1) pin generates the so0 latch status and thus the sb0 (or sb1) pin output status can be manipulated by setting the relt and cmdt bits. however, do not carry out this manipulation during serial transfer. control the sck0 pin output level in the output mode (internal system clock mode) by manipulating the p27 output latch (refer to 16.4.6 sck0/scl/p27 pin output manipulation ). 123 4 5 6 7 8 sck0 d7 d6 d5 d4 d3 d2 d1 d0 sb0 (sb1) csiif0 transfer start at the fallin g ed g e of sck0 end of transfer
313 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (3) other signals figure 16-12 shows relt and cmdt operations. figure 16-12. relt and cmdt operations (4) transfer start serial transfer is started by setting transfer data to the serial i/o shift register 0 (sio0) when the following two conditions are satisfied. ? serial interface channel 0 operation control bit (csie0) = 1 ? internal serial clock is stopped or sck0 is at high level after 8-bit serial transfer cautions 1. if csie0 is set to 1 after data write to sio0, transfer does not start. 2. because the n-ch transistor must be turned off for data reception, write ffh to sio0 in advance. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. (5) error detection in the 2-wire serial i/o mode, the serial bus sb0 (sb1) status being transmitted is fetched into the destination device, that is, sio0. thus, transmit error can be detected in the following way. (a) method of comparing sio0 data before transmission to that after transmission in this case, if two data differ from each other, a transmit error is judged to have occurred. (b) method of using the slave address register (sva) transmit data is set to both sio0 and sva and is transmitted. after termination of transmission, coi bit (match signal coming from the address comparator) of the serial operating mode register 0 (csim0) is tested. if 1, normal transmission is judged to have been carried out. if 0, a transmit error is judged to have occurred. relt cmdt so0 latch
314 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 16.4.4 i 2 c bus mode operation the i 2 c bus mode is provided for when communication operations are performed between a single master device and multiple slave devices. this mode configures a serial bus that includes only a single master device, and is based on the clocked serial i/o format with the addition of bus configuration functions, which allows the master device to communicate with a number of (slave) devices using only two lines: serial clock (scl) line and serial data bus (sda0 or sda1) line. consequently, when the user plans to configure a serial bus which includes multiple microcontrollers and peripheral devices, using this configuration results in reduction of the required number of port pins and on-board wires. in the i 2 c bus specification, the master sends start condition, data, and stop condition signals to slave devices through the serial data bus, while slave devices automatically detect and distinguish the type of signals due to the signal detection function incorporated as hardware. this simplifies i 2 c bus control sections in the application pro- gram. an example of a serial bus configuration is shown in figure 16-13. this system below is composed of cpus and peripheral ics having serial interface hardware that complies with the i 2 c bus specification. note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because open- drain buffers are used for the serial clock pin (scl) and the serial data bus pin (sda0 or sda1) on the i 2 c bus. the signals used in the i 2 c bus mode are described in table 16-4. figure 16-13. example of serial bus configuration using i 2 c bus scl sda0(sda1) scl sda0(sda1) scl sda0(sda1) scl sda slave ic slave cpu2 slave cpu1 master cpu v dd serial clock serial data bus v dd
315 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (1) i 2 c bus mode functions in the i 2 c bus mode, the following functions are available. (a) automatic identification of serial data slave devices automatically detect and identifies start condition, data, and stop condition signals sent in series through the serial data bus. (b) chip selection by specifying device addresses the master device can select a specific slave device connected to the i 2 c bus and communicate with it by sending in advance the address data corresponding to the destination device. (c) wake-up function when address data is sent from the master device, slave devices compare it with the value registered in their internal slave address registers. if the values in one of the slave devices match, the slave device internally generates an interrupt signal to terminate the current processing and communicates with the master device. therefore, cpus other than the selected slave device on the i 2 c bus can perform independent operations during the serial communication. (d) acknowledge signal (ack) control function the master device and a slave device send and receive acknowledge signals to confirm that the serial commu- nication has been executed normally. (e) wait signal (wait) control function when a slave device is preparing for data transmission or reception and requires more waiting time, the slave device outputs a wait signal on the bus to inform the master device of the wait status. (2) i 2 c bus definition this section describes the format of serial data communications and functions of the signals used in the i 2 c bus mode. first, the transfer timings of the start condition, data, and stop condition signals, which are output onto the signal data bus of the i 2 c bus, are shown in figure 16-14. figure 16-14. i 2 c bus serial data transfer timing the start condition, slave address, and stop condition signals are output by the master. the acknowledge signal (ack) is output by either the master or the slave device (normally by the device which has received the 8-bit data that was sent). a serial clock (scl) is continuously supplied from the master device. 1-7 8 9 1-7 8 9 1-7 8 9 address r/w ack data ack data ack scl start condition sda0(sda1) stop condition
316 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (a) start condition when the sda0 (sda1) pin level is changed from high to low while the scl pin is high, this transition is recognized as the start condition signal. this start condition signal, which is created using the scl and sda0 (or sda1) pins, is output from the master device to slave devices to initiate a serial transfer. see section 16.4.5, "cautions on use of i 2 c bus mode," for details of the start condition output. the start condition signal is detected by hardware incorporated in slave devices. figure 16-15. start condition (b) address the 7 bits following the start condition signal are defined as an address. the 7-bit address data is output by the master device to specify a specific slave from among those connected to the bus line. each slave device on the bus line must therefore have a different address. therefore, after a slave device detects the start condition, it compares the 7-bit address data received and the data of the slave address register (sva). after the comparison, only the slave device in which the data are a match becomes the communication partner, and subsequently performs communication with the master de- vice until the master device sends a start condition or stop condition signal. figure 16-16. address (c) transfer direction specification the 1 bit that follows the 7-bit address data will be sent from the master device, and it is defined as the transfer direction specification bit. if this bit is 0, it is the master device which will send data to the slave. if it is 1, it is the slave device which will send data to the master. figure 16-17. transfer direction specification h scl sda0(sda1) 1234567 a6 a5 a4 a3 a2 a1 a0 r/w address scl sda0(sda1) 234567 a6 a5 a4 a3 a2 a1 a0 r/w transfer direction specification scl 8 1 sda0(sda1)
317 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (d) acknowledge signal (ack) the acknowledge signal indicates that the transferred serial data has definitely been received. this signal is used between the sending side and receiving side devices for confirmation of correct data transfer. in princi- ple, the receiving side device returns an acknowledge signal to the sending device each time it receives 8-bit data. the only exception is when the receiving side is the master device and the 8-bit data is the last transfer data; the master device outputs no acknowledge signal in this case. the sending side that has tranferred 8-bit data waits for the acknowledge signal which will be sent from the receiving side. if the sending side device receives the acknowledge signal, which means a successful data transfer, it proceeds to the next processing. if this signal is not sent back from the slave device, this means that the data sent has not been received by the slave device, and therefore the master device outputs a stop condition signal to terminate subsequent transmissions. figure 16-18. acknowledge signal (e) stop condition if the sda0 (sda1) pin level changes from low to high while the scl pin is high, this transition is defined as a stop condition signal. the stop condition signal is output from the master to the slave device to terminate a serial transfer. the stop condition signal is detected by hardware incorporated in the slave device. figure 16-19. stop condition h scl sda0(sda1) 1234567 a6 a5 a4 a3 a2 a1 a0 r/w scl sda0 i sda1 j 9 8 ack
318 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (f) wait signal (wait) the wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. during the wait state, the slave device continues to output the wait signal by keeping the scl pin low to delay subsequent transfers. when the wait state is released, the master device can start the next transfer. for the releasing operation of slave devices, see section 16.4.5, "cautions on use of i 2 c bus mode." figure 16-20. wait signal (a) wait of 8 clock cycles (b) wait of 9 clock cycles scl of master device d2 d1 d0 ack d7 output b y manipulatin g ackt 6789 1 3 24 d6 d5 d4 set low because slave device drives low, though master device returns to hi-z state. no wait is inserted after 9th clock cycle. (and before master device starts next transfer.) scl of slave device scl sda0(sda1) scl of master device set low because slave device drives low, though master device returns to hi-z state. scl of slave device scl d2 d1 d0 ack d7 output based on the value set in acke in advance 6789 23 d6 d5 1 sda0(sda1)
319 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (3) register setting the i 2 c mode setting is performed by the serial operating mode register 0 (csim0), the serial bus interface control register (sbic), and the interrupt timing specify register (sint). (a) serial operating mode register 0 (csim0) csim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets 00h. the csim0 format is shown below, where the bits used in the i 2 c bus mode are shaded. r/w csim01 csim00 serial interface channel 0 clock selection 0 x input clock from off-chip to scl pin 1 0 8-bit timer register 2 (tm2) output note 2 1 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) r/w csim csim csim pm25 p25 pm26 p26 pm27 p27 operation start si0/sb0/sda0/ so0/sb1/sda1/ sck0/scl/p27 04 03 02 mode bit p25 pin function p26 pin function pin function 0 x 3-wire serial i/o mode (see section 16.4.2 "3-wire serial i/o mode operation") 1 1 0 x x 0 0 0 1 2-wire msb p25 sb1/sda1 sck0/scl note3 note3 serial i/o or (cmos i/o) (n-ch open- (n-ch open- i 2 c bus mode drain i/o) drain i/o) 1 1 1 0 0 x x 0 1 2-wire msb sb0/sda0 p26 sck0/scl note3 note3 serial i/o or (n-ch open- (cmos i/o) (n-ch open- i 2 c bus mode drain i/o) drain i/o) r/w wup wake-up function control 0 interrupt request signal generation with each serial transfer in any mode 1 in i 2 c bus mode, interrupt request signal is generated when the address data received after start condition detection (when cmdd = 1) matches data in slave address register. r coi slave address comparison result flag note 4 0 slave address register not equal to data in serial i/o shift register 0 1 slave address register equal to data in serial i/o shift register 0 r/w csie0 serial interface channel 0 operation control 0 stops operation. 1 enables operation. notes 1. bit 6 (coi) is a read-only bit. 2. in the i 2 c bus mode, the clock frequency is 1/16 of the clock frequency output by to2. 3. can be used freely as a port. 4. when csie0 = 0, coi is 0. remark: x: dont care 6543210 7 symbol csim0 address after reset r/w csie0 coi wup csim04 csim03 csim02 csim01 csim00 ff60h 00h r/w note 1
320 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (b) serial bus interface control register (sbic) sbic is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic to 00h. the sbic format is shown below, where the bits used in the i 2 c bus mode are shaded. r/w relt use for stop condition output. when relt = 1, so latch is set to 1. after so latch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w cmdt use for start condition output. when cmdt = 1, so latch is cleared to 0. after clearing so latch, automatically cleared to 0. also cleared to 0 when csie0 = 0. r reld stop condition detection 0 clear conditions ? when transfer start instruction is executed ? if sio0 and sva values do not match in address reception ? when csie0 = 0 ? when reset input is applied 1 setting condition ? when stop condition is detected r cmdd start condition detection 0 clear conditions ? when transfer start instruction is executed ? when stop condition is detected ? when csie0 = 0 ? when reset input is applied 1 setting condition ? when start condition is detected r/w ackt sda0 (sda1) is set to low after the set instruction execution (ackt = 1) before the next scl falling edge. used for generating an ack signal by software if the 8-clock wait mode is selected. cleared to 0 if csie0 = 0 when a transfer by the serial interface is started. r/w acke acknowledge signal automatic output control note 2 0 disabled (with ackt enabled). used when receiving data in the 8-clock wait mode or when transmitting data note 3 . 1 enabled. after completion of transfer, acknowledge signal is output in synchronization with the 9th falling edge of scl clock (automatically output when acke = 1). however, not automatically cleared to 0 after acknowl- edge signal output. used for reception when the 9-clock wait mode is selected. r ackd acknowledge detection 0 clear conditions ? when transfer start instruction is executed ? when csie0 = 0 ? when reset input is applied 1 set conditions ? when acknowledge signal is detected at the rising edge of scl clock after completion of transfer r/w note 4 control of n-ch open-drain output for transmission in i 2 c bus mode note 5 bsye 0 output enabled (transmission) 1 output disabled (reception) notes 1. bits 2, 3, and 6 (reld, cmdd, ackd) are read-only bits. 2. this setting must be performed prior to transfer start. 3. in the 8-clock wait mode, use ackt for output of the acknowledge signal after normal data reception. 4. the busy mode can be released by the start of a serial interface transfer or reception of an address signal. however, the bsye flag is not cleared. 5. when using the wake-up function, be sure to set bsye to 1. 6543210 7 symbol sbic bsye ackd acke address after reset r/w ackt cmdd reld cmdt relt ff61h 00h r/w note 1
321 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (c) interrupt timing specification register (sint) sint is set by the 1-bit or 8-bit memory manipulation instruction. reset input sets sint to 00h. the sint format is shown below, where the bits used in the i 2 c bus mode are shaded. r/w wat1 wat0 interrupt control by wait note 2 00 interrupt service request is generated on rise of 8th sck0 clock cycle (clock output is high impedance). 0 1 setting prohibited 1 0 used in i 2 c bus mode (8-clock wait) generates an interrupt service request on rise of 8th scl clock cycle. (in case of master device, scl pin is driven low after output of 8 clock cycles, to enter the wait state. in case of slave device, scl pin is driven low after input of 8 clock cycles, to require the wait state.) 1 1 used in i 2 c bus mode (9-clock wait) generates an interrupt service request on rise of 9th scl clock cycle. (in case of master device, scl pin is driven low after output of 9 clock cycles, to enter the wait state. in case of slave device, scl pin is driven low after input of 9 clock cycles, to require the wait state.) r/w wrel wait release control 0 indicates that the wait state has been released. 1 releases the wait state. automatically cleared to 0 after releasing the wait state. this bit is used to release the wait state set by means of wat0 and wat1. r/w clc clock level control 0 used in i 2 c bus mode. in cases other than serial transfer, scl pin output is driven low. 1 used in i 2 c bus mode. in cases other than serial transfer, scl pin output is set to high impedance. (clock line is held high.) used by master device to generate the start condition and stop condition signals. r/w svam sva bits used as slave address 0 bits 0 to 7 1 bits 1 to 7 r/w sic intcsi0 interrupt source selection note 3 0 csiif0 is set to 1 after end of serial interface channel 0 transfer. 1 csiif0 is set to 1 after end of serial interface channel 0 transfer or when stop condition is detected. r cld scl pin level note 4 0 low level 1 high level notes 1. bit 6 (cld) is read-only. 2. when the i 2 c bus mode is used, be sure to set 1 and 0, or 1 and 1 in wat0 and wat1, respectively. 3. when using the wake-up function in i 2 c mode, be sure to set sic to 1. 4. when csie0 = 0, cld is 0. remark sva: slave address register 6543210 7 symbol sint 0 cld sic address after reset r/w svam clc wrel wat1 wat0 ff63h 00h r/w note 1
322 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (4) various signals a list of signals in the i 2 c bus mode is given in table 16-4. table 16-4. signals in i 2 c bus mode signal name description start condition definition : sda0 (sda1) falling edge when scl is high note 1 function : indicates that serial communication starts and subsequent data are address data. signaled by : master signaled when : cmdt is set. affected flag(s) : cmdd (is set.) stop condition definition : sda0 (sda1) rising edge when scl is high note 1 function : indicates end of serial transmission. signaled by : master signaled when : relt is set. affected flag(s) : reld (is set) and cmdd (is cleared) acknowledge signal (ack) definition : low level of sda0(sda1) pin during one scl clock cycle after serial reception function : indicates completion of reception of 1 byte. signaled by : master or slave signaled when : ackt is set with acke = 1. affected flag(s) : ackd (is set.) wait (wait) definition : low-level signal output to scl function : indicates state in which serial reception is not possible. signaled by : slave signaled when : wat1, wat0 = 1x. affected flag(s) : none serial clock (scl) definition : synchronization clock for output of various signals function : serial communication synchronization signal. signaled by : master signaled when : see note 2 below. affected flag(s) : csiif0. also see note 3 below. address (a6 to a0) definition : 7-bit data synchronized with scl immediately after start condition signal function : indicates address value for specification of slave on serial bus. signaled by : master signaled when : see note 2 below. affected flag(s) : csiif0. also see note 3 below. transfer direction (r/w) definition : 1-bit data output in synchronization with scl after address output function : indicates whether data transmission or reception is to be performed. signaled by : master signaled when : see note 2 below. affected flag(s) : csiif0. also see note 3 below. data (d7 to d0)) definition : 8-bit data synchronized with scl, not immediately after start condition function : contains data actually to be sent. signaled by : master or slave signaled when : see note 2 below. affected flag(s) : csiif0. also see note 3 below. notes 1. the level of the serial clock can be controlled by clc of sint. 2. execution of instruction to write data to sio0 when csie0 = 1 (serial transfer start directive). in the wait state, the serial transfer operation will be started after the wait state is released. 3. if the 8-clock wait is selected when wup = 0, csiif0 is set at the rising edge of the 8th clock cycle of scl. if the 9-clock wait is selected when wup = 0, csiif0 is set at the rising edge of the 9th clock cycle of scl. if wup = 1, csiif0 is set only when an address is received and the address matches the slave address register (sva) value.
323 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (5) pin configurations the configurations of the serial clock pin (scl) and the serial data bus pins (sda0, sda1) are shown below. (a) scl pin for serial clock input/output dual-function pin. <1> master .... n-ch open-drain output <2> slave ....... schmitt input (b) sda0 (sda1) serial data input/output dual-function pin. uses n-ch open-drain output and schmitt-input buffers for both master and slave devices. note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because open- drain buffers are used for the serial clock pin (scl) and the serial data bus pin (sda0 or sda1) on the i 2 c bus. figure 16-21. pin configuration caution because the n-ch open-drain output must be disabled during data reception, set bsye of sbic to 1 before writing ffh to sio0. (6) address match detection method in the i 2 c mode, the master can select a specific slave device by sending slave address data. address match detection is performed automatically by the slave device hardware. a slave device address has a slave register (sva), and compares its contents and the slave address sent from the master device. if they match and the wake-up function specification (wup) bit is then 1, interrupt request flag (csiif0) is set. caution be sure to set the wup bit to 1 before the master device sends slave address data to slave devices. each slave device recognizes whether the slave device is selected or not by master device by comparing the content of the sva register (which is in each slave device) and the slave address data, which is sent by master device immediately after the start condition signal. only if the wup bit has been set to 1 when they match, the slave device generates intcsi0 signal. v dd v dd scl sda0(sda1) master device clock output (clock input) data output data input slave devices (clock output) clock input data output data input scl sda0(sda1)
324 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (7) error detection in the i 2 c bus mode, transmission error detection can be performed by the following methods because the serial bus sda0 (sda1) status during transmission is also taken into the sio0 register of the transmitting device. (a) comparison of sio0 data before and after transmission in this case, a transmission error is judged to have occurred if the two data values are different. (b) using the slave address register (sva) transmit data is set in sio0 and sva before transmission is performed. after transmission, the coi bit (match signal from the address comparator) of serial operating mode register 0 (csim0) is tested: "1" indicates normal transmission, and "0" indicates a transmission error. (8) communication operation in the i 2 c bus mode, the master selects the slave device to be communicated with from among multiple devices by outputting address data onto the serial bus. after the slave address data, the master sends the r/w bit which indicates the data transfer direction, and starts serial communication with the selected slave device. data communication timing charts are shown in figures 16-22 and 16-23. in the transmitting device, the shift register (sio0) shifts transmission data to the so latch in synchroniza- tion with the falling edge of the serial clock (scl), the so0 latch outputs the data on an msb-first basis from the sda0 or sda1 pin to the receiving device. in the receiving device, the data input from the sda0 or sda1 pin is taken into the shift register (sio0) in synchronization with the rising edge of scl. (9) start of transfer a serial transfer is started by setting transfer data in sio0 if the following two conditions have been satis- fied: (a) the serial interface channel 0 operation control bit (csie0) = 1. (b) after an 8-bit serial transfer, the internal serial clock is stopped or scl is low. cautions 1. be sure to set csie0 to 1 before writing data in sio0. setting csie0 to 1 after writing data in sio0 does not initiate transfer operation. 2. because the n-ch open-drain output must be disabled during data reception, set bsye of sbic to 1 before writing ffh to sio0. 3. if data is written to sio0 while the slave is in the wait state, that data is held. the transfer is started when scl is output after the wait state is cleared. when an 8-bit data transfer ends, serial transfer is stopped automatically and the interrupt request flag (csiif0) is set.
325 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 figure 16-22. data transmission from master to slave (both master and slave selected 9-clock wait) (1 of 3) (a) start condition to address master device operation transfer line slave device operation write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 scl sda0(sda1) sio0 address sio0 data l h l l l l l l 2 a6 1 3456789 12345 a5 a4 a3 a2 a1 a0 w ack d4 d5 d6 d7 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 sio0 ffh l h h l l h l l
326 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 figure 16-22. data transmission from master to slave (both master and slave selected 9-clock wait) (2 of 3) (b) data master device operation transfer line slave device operation write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 scl sda0(sda1) sio0 data sio0 data l h l l l l l l 2 d7 1 3456789 12345 d6 d5 d4 d3 d2 d1 ack d4 d5 d6 d7 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 sio0 ffh l h h l l h l l l l l ffh d0 678 d3 d2 d1 sio0
327 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 figure 16-22. data transmission from master to slave (both master and slave selected 9-clock wait) (3 of 3) (c) stop condition master device operation transfer line slave device operation write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 scl sda0(sda1) sio0 data sio0 address h l l l l l 2 d6 1 3456789 1234 d5 d4 d3 d2 d1 d0 ack a4 a5 a6 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 h h l l h l l sio0 ffh sio0 ffh d7 sio0 ffh
328 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 figure 16-23. data transmission from slave to master (both master and slave selected 9-clock wait) (1 of 3) (a) start condition to address master device operation transfer line slave device operation write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 scl sda0(sda1) sio0 address sio0 ffh l h l l l l 2 a6 1 3456789 12345 a5 a4 a3 a2 a1 a0 ack d4 d5 d6 d7 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 l l l h l l r sio0 data
329 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 figure 16-23. data transmission from slave to master (both master and slave selected 9-clock wait) (2 of 3) (b) data master device operation transfer line write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 scl sda0(sda1) sio0 ffh sio0 ffh l h l h h l l l 2 d7 1 3456789 12345 d6 d5 d4 d3 d2 d1 ack d4 d5 d6 d7 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 l l l l l h l l l l l d0 678 d3 d2 d1 slave device operation sio0 data sio0 data
330 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 figure 16-23. data transmission from slave to master (both master and slave selected 9-clock wait) (3 of 3) (c) stop condition master device operation transfer line write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 scl sda0(sda1) sio0 ffh sio0 address h l l l 2 d6 1 3456789 1234 d5 d4 d3 d2 d1 d0 nak a4 a5 a6 write sio0 coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 l l h l l sio0 ffh sio0 ffh d7 sio0 data slave device operation
331 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 16.4.5 cautions on use of i 2 c bus mode (1) start condition output (master) the scl pin normally outputs a low-level signal when no serial clock is output. it is necessary to change the scl pin to high in order to output a start condition signal. set 1 in clc of sint to drive the scl pin high. after setting clc, clear clc to 0 and return the scl pin to low. if clc remains 1, no serial clock is output. if it is the master device which outputs the start condition and stop condition signals, confirm that cld is set to 1 after setting clc to 1; a slave device may have set scl to low (wait state). figure 16-24. start condition output scl clc cmdt cld sda0(sda1)
332 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (2) slave wait release (slave transmission) the wait status of a slave is released by setting the wrel flag, which is bit 2 of the interrupt timing specify register (sint), or by executing an sio0 write instruction. if the slave sends data, the wait is immediately released by execution of an sio0 write instruction and the clock rises without the start transmission bit being output in the data line. therefore, manipulate the p27 output latch through the program as shown in figure 16-25 to transmit data correctly. at this time, control the low-level width (" a " in figure 16-25) of the first serial clock at the timing used for setting the p27 output latch to 1 after execution of an sio0 write instruction. in addition, if the acknowledge signal from the master is not output (if data transmission from the slave is completed), set 1 in the wrel flag of sint and release the wait. for these timings, see figure 16-23. figure 16-25. slave wait release (transmission) writing ffh to sio0 setting csiif0 setting ackd serial reception 9 a 23 a0 r ack d7 d6 d5 p27 output latch 1 setting csiif0 ack output serial transmission write data to sio0 p27 output latch 0 wait release software operation hardware operation scl software operation hardware operation transfer line master device operation slave device operation 1 sda0(sda1)
333 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (3) slave wait release (slave reception) the wait status of a slave is released by setting the wrel flag, which is bit 2 of the interrupt timing specify register (sint), or by executing an sio0 write instruction. when a slave receives data, if the scl line immediately enters a high-impedance state due to a write to sio0, the slave may not receive the first bit of the data sent from the master. this is because sio0 cannot start operation if the scl line is in a high-impedance state during execution of a write instruction to sio0 (until the next instruction execution is started). therefore, manipulate the p27 output latch through the program as shown in figure 16-26 to receive data correctly. for these timings, see figure 16-22. figure 16-26. slave wait release (reception) (4) reception completion of slave during processing of reception completion by a slave device, confirm the statuses of cmdd and coi (if cmdd = 1). this procedure is necessary to use the wake-up function normally. if an uncertain amount of data is sent from the master device, the slave device cannot determine whether the start condition signal or the data will be sent from the master. this may disable use of the wake-up function. writing data to sio0 setting csiif0 setting ackd serial transmission 923 a0 w ack d7 d6 d5 p27 output latch 1 setting csiif0 ack output serial reception write ffh to sio0 p27 output latch 0 wait release software operation hardware operation scl software operation hardware operation transfer line master device operation slave device operation 1 sda0(sda1) *
334 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 16.4.6 sck0/scl/p27 pin output manipulation the sck0/scl/p27 pin enables static output by manipulating software in addition to normal serial clock output. the number of serial clocks can be set by software (si0/sb0/sda0 and so0/sb1/sda1 pins are controlled with the relt and cmdt bits of serial bus interface control register (sbic)). the sck0/scl/p27 pin output should be manipulated as described below. (1) in 3-wire serial i/o mode and 2-wire serial i/o mode the sck0/scl/p27 pin output level is manipulated by the p27 output latch. <1> set serial operating mode register 0 (csim0) (sck0 pin is set in the output mode and serial operation is enabled). while serial transfer is suspended, sck0 is set to 1. <2> manipulate the content of the p27 output latch by executing the bit manipulation instruction. figure 16-27. sck0/scl/p27 pin configuration to internal circuit sck0/scl/p27 p27 output latch when csie0 = 1 and csim01 and csim00 are 1 and 0 , or 1 and 1. sck0 (1 when transfer stops) from serial clock control circuit set by bit manipulation instruction
335 chapter 16 serial interface channel 0 ( m pd78064y subseries) users manual u10105ej4v1um00 (2) in i 2 c bus mode the sck0/scl/p27 pin output level is manipulated by the clc bit of interrupt timing specify register (sint). <1> set serial operating mode register 0 (csim0) (scl pin is set in the output mode and serial operation is enabled). set 1 to the p27 output latch. while serial transfer is suspended, scl is set to 0. <2> manipulate the content of the clc bit of sint by executing the bit manipulation instruction. figure 16-28. sck0/scl/p27 pin configuration note the level of scl signal follows the contents of logic circuit shown in figure 16-29. figure 16-29. logic circuit of scl signal remarks 1. this figure shows the relationship of each signal, and does not show the internal circuit. 2. clc : bit 3 of interrupt timing specify register (sint) to internal circuit sck0/scl/p27 p27 output latch when csie0 = 1 and csim01 and csim00 are 1 and 0 , or 1 and 1. scl from serial clock control circuit set 1 note scl clc (set by bit manipulation instruction) serial clock (low level when transfer sto p s) wait request signal
336 users manual u10105ej4v1um00 [memo]
337 users manual u10105ej4v1um00 chapter 17 serial interface channel 2 17.1 serial interface channel 2 functions serial interface channel 2 has the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not carried out to reduce power consumption. (2) asynchronous serial interface (uart) mode in this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. a dedicated uart baud rate generator is incorporated, allowing communication over a wide range of baud rates. in addition, the baud rate can be defined by scaling the input clock to the asck pin. the midi standard baud rate (31.25 kbps) can be used by employing the dedicated uart baud rate generator. (3) 3-wire serial i/o mode (msb-first/lsb-first switchable) in this mode, 8-bit data transfer is performed using three lines: the serial clock (sck2), and serial data lines (si2, so2). in the 3-wire serial i/o mode, simultaneous transmission and reception is possible, increasing the data transfer processing speed. either the msb or lsb can be specified as the start bit for an 8-bit data serial transfer, allowing connection to devices using either as the start bit. the 3-wire serial i/o mode is useful for connection to peripheral i/os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75x series, 78k series, 17k series, etc.
338 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 17.2 serial interface channel 2 configuration serial interface channel 2 consists of the following hardware. table 17-1. serial interface channel 2 configuration item configuration register transmit shift register (txs) receive shift register (rxs) receive buffer register (rxb) control register serial operating mode register 2 (csim2) asynchronous serial interface mode register (asim) asynchronous serial interface status register (asis) baud rate generator control register (brgc)
339 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 figure 17-1. serial interface channel 2 block diagram note see figure 17-2 for the baud rate generator configuration. internal bus asynchronous serial interface mode register asynchronous serial interface status register receive buffer register (rxb/sio2) direction control circuit receive shift register (rxs) reception control circuit rxd/si2/ p70 txd/so2/ p71 intsr/intcsi2 csie2 csim 22 csck intser sck output control circuit baud rate generator f xx -f xx /2 10 internal bus csck sck intst baud rate generator control register note serial operating mode register 2 pe fe ove transmission control circuit pm71 isrm asck/ sck2/p72 pm72 direction control circuit transmit shift register (txs/sio2) rxe ps1 ps0 cl sl isrm txe sck 4 4 csie2 txe rxe mdl3 mdl2 mdl1 mdl0 tps3 tps2 tps1 tps0 *
340 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 figure 17-2. baud rate generator block diagram tps3 tps2 tps1 tps0 internal bus mdl3 mdl2 mdl1 mdl0 baud rate generator control register 4 txe csie2 5-bit counter selector selector decoder 1/2 selector transmit clock 1/2 selector receive clock match match mdl0-mdl3 5-bit counter rxe start bit detection selector f xx -f xx /2 10 tps0-tps3 sck csck asck/sck2/p72 4 4 start bit sampling clock
341 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (1) transmit shift register (txs) this register is used to set the transmit data. the data written in txs is transmitted as serial data. if the data length is specified as 7 bits, bits 0 to 6 of the data written in txs are transferred as transmit data. writing data to txs starts the transmit operation. txs is written to with an 8-bit memory manipulation instruction. it cannot be read. txs value is ffh after reset input. caution txs must not be written to during a transmit operation. txs and the receive buffer register (rxb) are allocated to the same address, and when a read is performed, the value of rxb is read. (2) receive shift register (rxs) this register is used to convert serial data input to the rxd pin to parallel data. when one byte of data is received, the receive data is transferred to the receive buffer register (rxb). rxs cannot be directly manipulated by a program. (3) receive buffer register (rxb) this register holds receive data. each time one byte of data is received, new receive data is transferred from the receive shift register (rxs). if the data length is specified as 7 bits, the receive data is transferred to bits 0 to 6 of rxb, and the msb of rxb is always set to 0. rxb is read with an 8-bit memory manipulation instruction. it cannot be written to. rxb value is ffh after reset input. caution rxb and the transmit shift register (txs) are allocated to the same address, and when a write is performed, the value is written to txs. (4) transmission control circuit this circuit performs transmit operation control such as the addition of a start bit, parity bit and stop bit to data written in the transmit shift register (txs) in accordance with the contents set in the asynchronous serial interface mode register (asim). (5) reception control circuit this circuit controls receive operations in accordance with the contents set in the asynchronous serial interface mode register (asim). it performs error checks for parity errors, etc., during a receive operation, and if an error is detected, sets a value in the asynchronous serial interface status register (asis) in accordance with the error contents.
342 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 17.3 serial interface channel 2 control registers serial interface channel 2 is controlled by the following four registers. ? serial operating mode register 2 (csim2) ? asynchronous serial interface mode register (asim) ? asynchronous serial interface status register (asis) ? baud rate generator control register (brgc) (1) serial operating mode register 2 (csim2) this register is set when serial interface channel 2 is used in the 3-wire serial i/o mode. csim2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim2 to 00h. figure 17-3. serial operating mode register 2 format 6543210 7 symbol csim2 csie2 0 0 0 0 csim 22 csck 0 ff72h 00h r/w address after reset r/w csck 0 1 clock selection in 3-wire serial i/o mode input clock from off-chip to sck2 pin dedicated baud rate generator output csim22 0 1 first bit specification msb lsb csie2 0 1 operation control in 3-wire serial i/o mode operation stopped operation enabled cautions 1. ensure that bit 0 and bit 3 to bit 6 are set to 0. 2. when uart mode is selected, csim2 should be set to 00h.
343 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (2) asynchronous serial interface mode register (asim) this register is set when serial interface channel 2 is used in the asynchronous serial interface mode. asim is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim to 00h. figure 17-4. asynchronous serial interface mode register format 6543210 7 symbol asim txe rxe ps1 ps0 cl sl isrm sck ff70h 00h r/w address after reset r/w sck 0 1 clock selection in asynchronous serial interface mode input clock from off-chip to asck pin dedicated baud rate generator output note isrm 0 1 control of reception completion interrupt in case of error generation reception completion interrupt generated in case of error generation reception completion interrupt not generated in case of error generation sl transmit data stop bit length specification cl 1 character length specification 7 bits 8 bits rxe 0 1 receive operation control receive operation stopped receive operation enabled txe 0 1 transmit operation control transmit operation stopped transmit operation enabled ps1 0 1 0 1 bit 1 2 bits 0 parity bit specification no parity even parity ps0 0 1 0 parity always added in transmission no parity test in reception (parity error not generated) 0 1 1 odd parity 0 note when sck is set to 1 and the baud rate generator output is selected, the asck pin can be used as an input/output port. cautions 1. when the 3-wire serial i/o mode is selected, 00h should be set in asim. 2. the serial transmit/receive operation must be stopped before changing the operating mode.
344 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 table 17-2. serial interface channel 2 operating mode settings (1) operation stop mode (2) 3-wire serial i/o mode (3) asynchronous serial interface mode notes 1. can be used freely as port function. 2. can be used as p70 (cmos input/output) when only transmitter is used. remark x: don't care p72/sck2 /asck pin functions p71/so2 /txd pin functions p70/si2 /rxd pin functions shift clock start bit txe rxe sck csie2 csim22 csck pm70 p70 pm71 p71 pm72 p72 asim csim2 0 0x 0xx x note1 x note1 x note1 x note1 x note1 x note1 p70 p71 p72 other than above setting prohibited p72/sck2 /asck pin functions p71/so2 /txd pin functions p70/si2 /rxd pin functions shift clock start bit txe rxe sck csie2 csim22 csck pm70 p70 pm71 p71 pm72 p72 asim csim2 0 00 1 1 0 1 0 1 0 1 1 note2 x note2 0 11 0 1 0 x 1 x 1 msb lsb external clock internal clock external clock internal clock si2 si2 so2 (cmos output) sck2 input sck2 output sck2 input sck2 output other than above setting prohibited note2 note2 so2 (cmos output) p72/sck2 /asck pin functions p71/so2 /txd pin functions p70/si2 /rxd pin functions shift clock start bit txe rxe sck csie2 csim22 csck pm70 p70 pm71 p71 pm72 p72 asim csim2 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 x note1 x note1 0 11 1 x x lsb external clock internal clock external clock internal clock external clock internal clock p70 txd (cmos output) asck input p72 asck input p72 asck input p72 p71 note1 x note 1 x 1 0 1 0 1 1 1 x x x note1 note 1 x rxd note 1 x note 1 x 01 1x txd (cmos output) note 1 x note 1 x other than above setting prohibited
345 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (3) asynchronous serial interface status register (asis) this is a register which displays the type of error when a reception error is generated in the asynchronous serial interface mode. asis is read with a 1-bit or 8-bit memory manipulation instruction. in 3-wire serial i/o mode, the contents of the asis are undefined. reset input sets asis to 00h. figure 17-5. asynchronous serial interface status register format pe 6543210 7 symbol asis 0 0 0 0 0 fe ove ff71h 00h r address after reset r/w ove 0 1 overrun error flag overrun error not generated overrun error generated note 1 (when next receive operation is completed before data from receive buffer register is read) fe 0 1 framing error flag framing error not generated framing error generated note 2 (when stop bit is not detected) pe 0 1 parity error flag parity error not generated parity error generated (when transmit data parity does not match) notes 1. the receive buffer register (rxb) must be read when an overrun error is generated. overrun errors will continue to be generated until rxb is read. 2. even if the stop bit length has been set as 2 bits by bit 2 (sl) of the asynchronous serial interface mode register, only single stop bit detection is performed during reception.
346 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (4) baud rate generator control register (brgc) this register sets the serial clock for serial interface channel 2. brgc is set with an 8-bit memory manipulation instruction. reset input sets brgc to 00h. figure 17-6. baud rate generator control register format (1/2) note can only be used in 3-wire serial i/o mode. remarks 1. f sck : 5-bit counter source clock 2. k : value set in mdl0 to mdl3 (0 k 14) baud rate generator input clock selection mdl3 mdl2 mdl1 mdl0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f sck /16 f sck /17 f sck /18 f sck /19 f sck /20 f sck /21 f sck /22 f sck /23 f sck /24 f sck /25 f sck /26 f sck /27 f sck /28 f sck /29 f sck /30 f sck note 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6543210 7 symbol brgc tps3 tps2 tps1 tps0 mdl3 mdl2 mdl1 mdl0 ff73h 00h r/w address after reset r/w k
347 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 figure 17-6. baud rate generator control register format (2/2) 5-bit counter source clock selection tps3 tps2 tps1 tps0 n mcs=1 mcs=0 0000f xx /2 10 f xx /2 10 (4.9 khz) f x /2 11 (2.4 khz) 11 0101f xx f x (5.0 mhz) f x /2 (2.5 mhz) 1 0110f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 2 0111f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 3 1000f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 4 1001f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 5 1010f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 6 1011f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 7 1100f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 8 1101f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 9 1110f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) 10 other than above setting prohibited caution when a write is performed to brgc during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. therefore, brgc must not be written to during a communication operation. remarks 1. f x : main system clock oscillation frequency 2. f xx : main system clock frequency (f x or f x /2) 3. mcs : oscillation mode selection register bit 0 4. n : value set in tps0 to tps3 (1 n 11) 5. figures in parentheses apply to operation with f x =5.0 mhz
348 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 the baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the asck pin. (a) generation of baud rate transmit/receive clock by means of main system clock the transmit/receive clocks generated by scaling the main system clock. the baud rate generated from the main system clock is found from the following expression. [baud rate] = [hz] f x : main system clock oscillation frequency f xx : main system clock frequency (fx or fx/2) n : value set in tps0 to tps3 (1 n 11) k : value set in mdl0 to mdl3 (0 k 14) table 17-3. relation between main system clock and baud rate fx=5.0 mhz fx=4.19 mhz mcs=1 mcs=0 mcs=1 mcs=0 brgc set value error (%) brgc set value error (%) brgc set value error (%) brgc set value error (%) 75 C 00h 1.73 0bh 1.14 ebh 1.14 110 06h 0.88 e6h 0.88 03h C2.01 e3h C2.01 150 00h 1.73 e0h 1.73 ebh 1.14 dbh 1.14 300 e0h 1.73 d0h 1.73 dbh 1.14 cbh 1.14 600 d0h 1.73 c0h 1.73 cbh 1.14 bbh 1.14 1200 c0h 1.73 b0h 1.73 bbh 1.14 abh 1.14 2400 b0h 1.73 a0h 1.73 abh 1.14 9bh 1.14 4800 a0h 1.73 90h 1.73 9bh 1.14 8bh 1.14 9600 90h 1.73 80h 1.73 8bh 1.14 7bh 1.14 19200 80h 1.73 70h 1.73 7bh 1.14 6bh 1.14 31250 74h 0 64h 0 71h C1.31 61h C1.31 38400 70h 1.73 60h 1.73 6bh 1.14 5bh 1.14 76800 60h 1.73 50h 1.73 5bh 1.14 remark mcs: oscillation mode selection register bit 0 f xx 2 n (k+16) baud rate (bps) *
349 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (b) generation of baud rate transmit/receive clock by means of external clock from asck pin the transmit/receive clock is generated by scaling the clock input from the asck pin. the baud rate generated from the clock input from the asck pin is obtained with the following expression. [baud rate] = [hz] f asck : frequency of clock input to asck pin k : value set in mdl0 to mdl3 (0 k 14) table 17-4. relation between asck pin input frequency and baud rate (when brgc is set to 00h) baud rate (bps) asck pin input frequency 75 2.4 khz 110 3.52 khz 150 4.8 khz 300 9.6 khz 600 19.2 khz 1200 38.4 khz 2400 76.8 khz 4800 153.6 khz 9600 307.2 khz 19200 614.4 khz 31250 1000.0 khz 38400 1228.8 khz f asck 2 (k+16)
350 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 17.4 serial interface channel 2 operation serial interface channel 2 has the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode 17.4.1 operation stop mode in the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced. in the operation stop mode, the p70/si2/rxd, p71/so2/txd and p72/sck2/asck pins can be used as normal input/ output ports. (1) register setting operation stop mode settings are performed using serial operating mode register 2 (csim2) and the asynchronous serial interface mode register (asim). (a) serial operating mode register 2 (csim2) csim2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim2 to 00h. the bit used in the operation stop mode is indicated by shading. csim 22 6543210 7 symbol csim2 csie2 0 0 0 0 csck 0 ff72h 00h r/w address after reset r/w csie2 0 1 operation control in 3-wire serial i/o mode operation stopped operation enabled caution ensure that bit 0 and bit 3 to bit 6 are set to 0.
351 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (b) asynchronous serial interface mode register (asim) asim is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim to 00h. the bits used in the operation stop mode are indicated by shading. sl 6543210 7 symbol asim txe rxe ps1 ps0 cl isrm sck ff70h 00h r/w address after reset r/w rxe 0 1 receive operation control receive operation stopped receive operation enabled txe 0 1 transmit operation control transmit operation stopped transmit operation enabled
352 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 17.4.2 asynchronous serial interface (uart) mode in this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. a dedicated uart baud rate generator is incorporated, allowing communication over a wide range of baud rates. in addition, the baud rate can be defined by scaling the input clock to the asck pin. the midi standard baud rate (31.25 kbps) can be used by employing the dedicated uart baud rate generator. (1) register setting uart mode settings are performed using serial operating mode register 2 (csim2), the asynchronous serial interface mode register (asim), the asynchronous serial interface status register (asis), and the baud rate generator control register (brgc). (a) serial operating mode register 2 (csim2) csim2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim2 to 00h. the bits used in the uart mode are indicated by shading. when the uart mode is selected, 00h should be set in csim2. 6543210 7 symbol csim2 csie2 0 0 0 0 csim 22 csck 0 csck 0 1 clock selection in 3-wire serial i/o mode input clock from off-chip to sck2 pin dedicated baud rate generator output csim22 0 1 first bit specification msb lsb csie2 0 1 operation control in 3-wire serial i/o mode operation stopped operation enabled ff72h 00h r/w address after reset r/w caution ensure that bit 0 and bit 3 to bit 6 are set to 0.
353 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (b) asynchronous serial interface mode register (asim) asim is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim to 00h. the bits used in the uart mode are indicated by shading. 6543210 7 symbol asim txe rxe ps1 ps0 cl sl isrm sck ff70h 00h r/w address after reset r/w sck 0 1 clock selection in asynchronous serial interface mode input clock from off-chip to asck pin dedicated baud rate generator output note isrm 0 1 control of reception completion interrupt in case of error generation reception completion interrupt generated in case of error generation reception completion interrupt not generated in case of error generation sl transmit data stop bit length specification cl 1 character length specification 7 bits 8 bits rxe 0 1 receive operation control receive operation stopped receive operation enabled txe 0 1 transmit operation control transmit operation stopped transmit operation enabled ps1 0 1 0 1 bit 1 2 bits 0 parity bit specification no parity even parity ps0 0 1 0 parity always added in transmission no parity test in reception (parity error not generated) 0 1 1 odd parity 0 note when sck is set to 1 and the baud rate generator output is selected, the asck pin can be used as an input/output port. caution the serial transmit/receive operation must be stopped before changing the operating mode.
354 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (c) asynchronous serial interface status register (asis) asis is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asis to 00h. the bits used in the uart mode are indicated by shading. pe 6543210 7 symbol asis 0 0 0 0 0 fe ove ff71h 00h r address after reset r/w ove 0 1 overrun error flag overrun error not generated overrun error generated note 1 (when next receive operation is completed before data from receive buffer register is read) fe 0 1 framing error flag framing error not generated framing error generated note 2 (when stop bit is not detected) pe 0 1 parity error flag parity error not generated parity error generated (when transmit data parity does not match) notes 1. the receive buffer register (rxb) must be read when an overrun error is generated. overrun errors will continue to be generated until rxb is read. 2. even if the stop bit length has been set as 2 bits by bit 2 (sl) of the asynchronous serial interface mode register, only single stop bit detection is performed during reception.
355 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (d) baud rate generator control register (brgc) brgc is set with an 8-bit memory manipulation instruction. reset input sets brgc to 00h. the bits used in the uart mode are indicated by shading. baud rate generator input clock selection mdl3 mdl2 mdl1 mdl0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 f sck /16 f sck /17 f sck /18 f sck /19 f sck /20 f sck /21 f sck /22 f sck /23 f sck /24 f sck /25 f sck /26 f sck /27 f sck /28 f sck /29 f sck /30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6543210 7 symbol brgc tps3 tps2 tps1 tps0 mdl3 mdl2 mdl1 mdl0 ff73h 00h r/w address after reset r/w k remark f sck : 5-bit counter source clock k : value set in mdl0 to mdl3 (0 k 14) (continued)
356 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 5-bit counter source clock selection tps3 tps2 tps1 tps0 n mcs=1 mcs=0 0000f xx /2 10 f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) 11 0101f xx f x (5.0 mhz) f x /2 (2.5 mhz) 1 0110f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 2 0111f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 3 1000f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 4 1001f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 5 1010f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 6 1011f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 7 1100f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 8 1101f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 9 1110f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) 10 other than above setting prohibited caution when a write is performed to brgc during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. therefore, brgc must not be written to during a communication operation. remarks 1. f x : main system clock oscillation frequency 2. f xx : main system clock frequency (f x or f x /2) 3. mcs : oscillation mode selection register bit 0 4. n : value set in tps0 to tps3 (1 n 11) 5. figures in parentheses apply to operation with f x = 5.0 mhz.
357 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 the baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the asck pin. (i) generation of baud rate transmit/receive clock by means of main system clock the transmit/receive clock is generated by scaling the main system clock. the baud rate generated from the main system clock is obtained with the following expression. [baud rate] = [hz] f x : main system clock oscillation frequency f xx : main system clock frequency (fx or fx/2) n : value set in tps0 to tps3 (1 n 11) k : value set in mdl0 to mdl3 (0 k 14) table 17-5. relation between main system clock and baud rate fx=5.0 mhz fx=4.19 mhz mcs=1 mcs=0 mcs=1 mcs=0 brgc set value error (%) brgc set value error (%) brgc set value error (%) brgc set value error (%) 75 C 00h 1.73 0bh 1.14 ebh 1.14 110 06h 0.88 e6h 0.88 03h C2.01 e3h C2.01 150 00h 1.73 e0h 1.73 ebh 1.14 dbh 1.14 300 e0h 1.73 d0h 1.73 dbh 1.14 cbh 1.14 600 d0h 1.73 c0h 1.73 cbh 1.14 bbh 1.14 1200 c0h 1.73 b0h 1.73 bbh 1.14 abh 1.14 2400 b0h 1.73 a0h 1.73 abh 1.14 9bh 1.14 4800 a0h 1.73 90h 1.73 9bh 1.14 8bh 1.14 9600 90h 1.73 80h 1.73 8bh 1.14 7bh 1.14 19200 80h 1.73 70h 1.73 7bh 1.14 6bh 1.14 31250 74h 0 64h 0 71h C1.31 61h C1.31 38400 70h 1.73 60h 1.73 6bh 1.14 5bh 1.14 76800 60h 1.73 50h 1.73 5bh 1.14 remark mcs: oscillation mode selection register bit 0 f xx 2 n (k+16) baud rate (bps) *
358 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (ii) generation of baud rate transmit/receive clock by means of external clock from asck pin the transmit/receive clock is generated by scaling the clock input from the asck pin. the baud rate generated from the clock input from the asck pin is obtained with the following expression. [baud rate] = [hz] f asck : frequency of clock input to asck pin k : value set in mdl0 to mdl3 (0 k 14) table 17-6. relation between asck pin input frequency and baud rate (when brgc is set to 00h) baud rate (bps) asck pin input frequency 75 2.4 khz 110 3.52 khz 150 4.8 khz 300 9.6 khz 600 19.2 khz 1200 38.4 khz 2400 76.8 khz 4800 153.6 khz 9600 307.2 khz 19200 614.4 khz 31250 1000.0 khz 38400 1228.8 khz 2 (k+16) f asck
359 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (2) communication operation (a) data format the transmit/receive data format is as shown in figure 17-7. one data frame consists of a start bit, character bits, parity bit and stop bit(s). the specification of character bit length, parity selection, and specification of stop bit length for each data frame is carried out with asynchronous serial interface mode register (asim). figure 17-7. asynchronous serial interface transmit/receive data format d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit start bit one data frame ? start bits ................. 1 bit ? character bits ......... 7 bits/8 bits ? parity bits ................ even parity/odd parity/0 parity/no parity ? stop bit(s) ................ 1 bit/2 bits when 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always "0". the serial transfer rate is selected by means of the asynchronous serial interface mode register and the baud rate generator control register. if a serial data receive error is generated, the receive error contents can be determined by reading the status of the asynchronous serial interface status register (asis). *
360 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (b) parity types and operation the parity bit is used to detect a bit error in the communication data. normally, the same kind of parity bit is used on the transmitting side and the receiving side. with even parity and odd parity, a one-bit (odd number) error can be detected. with 0 parity and no parity, an error cannot be detected. (i) even parity ? at transmission control is executed so that the number of bits with a value of "1" contained in the transmit data including parity bit is an even number. the parity bit value should be as follows. the number of bits with a value of "1" is an odd number in transmit data : 1 the number of bits with a value of "1" is an even number in transmit data : 0 ? at reception the number of bits with a value of "1" contained in the receive data including parity bit are counted, and if this is an odd number, a parity error is generated. (ii) odd parity ? at transmission conversely to the situation with even parity, control is executed so that the number of bits with a value of "1" contained in the transmit data including parity bit is an odd number. the parity bit value should be as follows. the number of bits with a value of "1" is an odd number in transmit data : 0 the number of bits with a value of "1" is an even number in transmit data : 1 ? at reception the number of bits with a value of "1" contained in the receive data including parity bit are counted, and if this is an even number, a parity error is generated. (iii) 0 parity when transmitting, the parity bit is set to "0" irrespective of the transmit data. at reception, a parity bit check is not performed. therefore, a parity error is not generated, irrespective of whether the parity bit is set to "0" or "1". (iv) no parity a parity bit is not added to the transmit data. at reception, data is received assuming that there is no parity bit. since there is no parity bit, a parity error is not generated.
361 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (c) transmission a transmit operation is started by writing transmit data to the transmit shift register (txs). the start bit, parity bit and stop bit(s) are added automatically. when the transmit operation starts, the data in the transmit shift register (txs) is shifted out, and when the transmit shift register (txs) is empty, a transmission completion interrupt (intst) is generated. figure 17-8. asynchronous serial interface transmission completion interrupt timing (a) stop bit length: 1 (b) stop bit length: 2 caution rewriting of the asynchronous serial interface mode register (asim) should not be performed during a transmit operation. if rewriting of the asim register is performed during transmission, subsequent transmit operations may not be possible (the normal state is restored by reset input). it is possible to determine whether transmission is in progress by software by using a transmission completion interrupt (intst) or the interrupt request flag (stif) set by the intst. d1 d2 d6 d7 parity d0 txd (output) intst stop start d1 d2 d6 d7 parity d0 txd (output) intst stop start
362 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (d) reception when the rxe bit of the asynchronous serial interface mode register (asim) is set (1), a receive operation is enabled and sampling of the rxd pin input is performed. rxd pin input sampling is performed using the serial clock specified by asim. when the rxd pin input becomes low, the 5-bit counter starts counting, and at the time when the half time determined by specified baud rate has passed, the data sampling start timing signal is output. if the rxd pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 5-bit counter is initialized and starts counting, and data sampling is performed. when character data, a parity bit and one stop bit are detected after the start bit, reception of one frame of data ends. when one frame of data has been received, the receive data in the shift register is transferred to the receive buffer register (rxb), and a reception completion interrupt (intsr) is generated. if an error is generated, the receive data in which the error was generated is still transferred to rxb, and intsr is generated. if the rxe bit is reset (0) during the receive operation, the receive operation is stopped immediately. in this case, the contents of rxb and asis are not changed, and intsr and intser are not generated. figure 17-9. asynchronous serial interface reception completion interrupt timing caution the receive buffer register (rxb) must be read even if a receive error is generated. if rxb is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely. d1 d2 d6 d7 parity d0 rxd (input) intsr stop start
363 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (e) receive errors three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. the data reception result error flag is set in the asynchronous serial interface status register (asis) and at the same time a receive error interrupt (intser) is generated. receive error causes are shown in table 17-7. it is possible to determine what kind of error was generated during reception by reading the contents of the asynchronous serial interface status register (asis) in the reception error interrupt servicing (intser) (see figures 17-9 and 17-10 ). the contents of asis are reset (0) by reading the receive buffer register (rxb) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). table 17-7. receive error causes receive errors cause parity error transmission-time parity specification and reception data parity do not match framing error stop bit not detected overrun error reception of next data is completed before data is read from receive register buffer figure 17-10. receive error timing cautions 1. the contents of the asis register are reset (0) by reading the receive buffer register (rxb) or receiving the next data. to ascertain the error contents, asis must be read before reading rxb. 2. the receive buffer register (rxb) must be read even if a receive error is generated. if rxb is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely. d1 d2 d6 d7 parity d0 rxd (input) intsr stop start intser
364 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (3) uart mode cautions (a) when bit 7 (txe) of the asynchronous serial interface mode register (asim) is cleared during transmission, be sure to set the transmit shift register (txs) to ffh, then set the txe to 1 before executing the next transmission. (b) when bit 6 (rxe) of the asynchronous serial interface mode register (asim) is cleared during reception, receive buffer register (rxb) and receive completion interrupt (intsr) are as follows. when rxe is set to 0 at a time indicated by <1> , rxb holds the previous data and does not generate intsr. when rxe is set to 0 at a time indicated by <2> , rxb renews the data and does not generate intsr. when rxe is set to 0 at a time indicated by <3> , rxb renews the data and generates intsr. parity rxd pin rxb intsr <3> <1> <2>
365 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 17.4.3 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connection of peripheral i/os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75x series, 78k series, 17k series, etc. communication is performed using three lines: the serial clock (sck2), serial output (so2), and serial input (si2). (1) register setting 3-wire serial i/o mode settings are performed using serial operating mode register 2 (csim2), the asynchro- nous serial interface mode register (asim), and the baud rate generator control register (brgc). (a) serial operating mode register 2 (csim2) csim2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim2 to 00h. the bits used in the 3-wire serial i/o mode are indicated by shading. caution ensure that bit 0 and bit 3 to bit 6 are set to 0. 6543210 7 symbol csim2 csie2 0 0 0 0 csim 22 csck 0 csck 0 1 clock selection in 3-wire serial i/o mode input clock from off-chip to sck2 pin dedicated baud rate generator output csim22 0 1 first bit specification msb lsb csie2 0 1 operation control in 3-wire serial i/o mode operation stopped operation enabled ff72h 00h r/w address after reset r/w *
366 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (b) asynchronous serial interface mode register (asim) asim is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim to 00h. the bits used in the 3-wire serial i/o mode are indicated by shading. when the 3-wire serial i/o mode is selected, 00h should be set in asim. 6543210 7 symbol asim txe rxe ps1 ps0 cl sl isrm sck ff70h 00h r/w address after reset r/w sck 0 1 clock selection in asynchronous serial interface mode input clock from off-chip to asck pin dedicated baud rate generator output isrm 0 1 control of reception completion interrupt in case of error generation reception completion interrupt generated in case of error generation reception completion interrupt not generated in case of error generation sl transmit data stop bit length specification cl 1 character length specification 7 bits 8 bits rxe 0 1 receive operation control receive operation stopped receive operation enabled txe 0 1 transmit operation control transmit operation stopped transmit operation enabled ps1 0 1 0 1 bit 1 2 bits 0 parity bit specification no parity even parity ps0 0 1 0 parity always added in transmission no parity test in reception (parity error not generated) 0 1 1 odd parity 0
367 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (c) baud rate generator control register (brgc) brgc is set with an 8-bit memory manipulation instruction. reset input sets brgc to 00h. the bits used in the uart mode are indicated by shading. baud rate generator input clock selection mdl3 mdl2 mdl1 mdl0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f sck /16 f sck /17 f sck /18 f sck /19 f sck /20 f sck /21 f sck /22 f sck /23 f sck /24 f sck /25 f sck /26 f sck /27 f sck /28 f sck /29 f sck /30 f sck 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6543210 7 symbol brgc tps3 tps2 tps1 tps0 mdl3 mdl2 mdl1 mdl0 ff73h 00h r/w address after reset r/w k remark f sck : 5-bit counter source clock k : value set in mdl0 to mdl3 (0 k 14)
368 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 5-bit counter source clock selection tps3 tps2 tps1 tps0 n mcs=1 mcs=0 0000f xx /2 10 f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) 11 0101f xx f x (5.0 mhz) f x /2 (2.5 mhz) 1 0110f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 2 0111f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 3 1000f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 4 1001f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 5 1010f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 6 1011f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 7 1100f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 8 1101f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 9 1110f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) 10 other than above setting prohibited caution when a write is performed to brgc during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. therefore, brgc must not be written to during a communication operation. remarks 1. f x : main system clock oscillation frequency 2. f xx : main system clock frequency (f x or f x /2) 3. mcs : oscillation mode selection register bit 0 4. n : value set in tps0 to tps3 (1 n 11) 5. figures in parentheses apply to operation with f x = 5.0 mhz.
369 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 when the internal clock is used as the serial clock in the 3-wire serial i/o mode, set brgc as described below. brgc setting is not required if an external serial clock is used. (i) when the baud rate generator is not used: select a serial clock frequency with tps0-tps3. be sure then to set mdl0 to mdl3 to 1,1,1,1. the serial clock frequency becomes the same as the source clock frequency for the 5-bit counter. (ii) when the baud rate generator is used: select a serial clock frequency with mdl0-mdl3 and tps0-tps3. be sure then to set mdl0 to mdl3 to a value other than 1,1,1,1. the serial clock frequency is calculated by the following formula: serial clock frequency= [h z ] f x : main system clock oscillation frequency f xx : main system clock frequency (f x or f x /2) n : value set in tps0 to tps3 (1 n 11) k : value set in mdl0 to mdl3 (0 k 14) f xx 2 n x (k + 16)
370 chapter 17 serial interface channel 2 users manual u10105ej4v1um00 (2) communication operation in the 3-wire serial i/o mode, data transmission/reception is performed in 8-bit units. data is transmitted/ received bit by bit in synchronization with the serial clock. transmit shift register (txs/sio2) and receive shift register (rxs) shift operations are performed in synchronization with the fall of the serial clock (sck2). then transmit data is held in the so2 latch and output from the so2 pin. also, receive data input to the si2 pin is latched in the receive buffer register (rxb/sio2) on the rise of sck2. at the end of an 8-bit transfer, the operation of the transmit shift register (txs/sio2) or receive shift register (rxs) stops automatically, and the interrupt request flag (srif) is set. figure 17-11. 3-wire serial i/o mode timing (3) transfer start serial transfer is started by setting transfer data to the transmission shift register (txs/sio2) when the following two conditions are satisfied. ? serial interface channel 2 operation control bit (csie2) =1 ? internal serial clock is stopped or sck2 is a high level after 8-bit serial transfer. caution if csie2 is set to "1" after data write to txs/sio2, transfer does not start. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (srif) is set. si2 sck2 12345678 di7 di6 di5 di4 di3 di2 di1 di0 so2 do7 do6 do5 do4 do3 do2 do1 do0 srif transfer start at the fallin g ed g e of sck2 end of transfer *
371 users manual u10105ej4v1um00 chapter 18 lcd controller/driver 18.1 lcd controller/driver functions the functions of the lcd controller/driver incorporated in the m pd78064, 78064y subseries are shown below. (1) automatic output of segment signals and common signals is possible by automatic reading of the display data memory. (2) any of five display modes can be selected. ? static ? 1/2 duty (1/2 bias) ? 1/3 duty (1/2 bias) ? 1/3 duty (1/3 bias) ? 1/4 duty (1/3 bias) (3) any of four frame frequencies can be selected in each display mode. (4) maximum of 40 segment signal outputs (s0 to s39); 4 common signal outputs (com0 to com3). sixteen of the segment signal outputs can be switched to input/output ports in units of 2 (p80/s39 to p87/ s32, p90/s31 to p97/s24). (5) in mask rom versions, split resistors for lcd drive voltage generation can be incorporated by mask option. (6) operation on the subsystem clock is also possible. the maximum number of displayable pixels in each display mode is shown in table 18-1. table 18-1. maximum number of display pixels bias method time division common signals used maximum number of pixels note C static com0 (com1, 2, 3) 40 (40 segments x 1 common) 1 1/2 2 com0, com1 80 (40 segments x 2 commons) 2 3 com0-com2 120 (40 segments x 3 commons) 3 1/3 3 4 com0-com3 160 (40 segments x 4 commons) 4 notes 1. 5 digits on type lcd panel with 8 segments/digit. 2. 10 digits on type lcd panel with 4 segments/digit. 3. 13 digits on type lcd panel with 3 segments/digit. 4. 20 digits on type lcd panel with 2 segments/digit.
372 chapter 18 lcd controller/driver users manual u10105ej4v1um00 18.2 lcd controller/driver configuration the lcd controller/driver is composed of the following hardware. table 18-2. lcd controller/driver configuration item configuration display outputs segment signals : 40 dedicated segment signals: 24 segment signal/input/output port dual function: 16 common signals : 4 (com0 to com3) control registers lcd display mode register (lcdm) lcd display control register (lcdc) figure 18-1. lcd controller/driver block diagram notes 1. selector 2. segment driver internal bus display data memory note 1 note 1 note 1 note 1 note 1 fa7fh fa7eh fa68h fa67h fa66h fa58h 0 1 2 3 0 1 2 30 1 2 30 1 2 30 1 2 3 0 1 2 3 note 1 0 1 2 3 4 5 6 70 1 2 3 4 5 6 70 1 2 3 4 5 6 70 1 2 3 4 5 6 70 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 note 2 note 2 note 2 s0 s1 s23 s24/p97 s25/p96 lcd on lcd m6 lcd m5 lcd m4 lcd m2 lcd m1 lcd m0 lcd c7 lcd c6 lcd c5 lcd c4 leps lips lcd mode register lcd display control register 33 42 lcd clock selector timing controller f lcd segment selector common driver lcd drive voltage controller v lc2 v lc1 v lc0 bias s39/p80 com3 com2 com1 com0 p98 output buffer p80 output buffer p96 output buffer note 2 note 2 note 2
373 chapter 18 lcd controller/driver users manual u10105ej4v1um00 figure 18-2. lcd clock select circuit block diagram remarks 1. the clock timer includes the circuit enclosed with the dotted line. 2. lcdcl : lcd clock 3. f ldc : lcd clock frequency f xx /2 8 f xt f w clear prescaler f w /2 6 prescaler f lcd /2 3 f lcd /2 2 f lcd /2 f lcd tcl24 tmc21 lcdm6 lcdm5 lcdm4 3 lcdcl lcd display mode register watch timer mode control register timer clock select register 2 internal bus selector selector
374 chapter 18 lcd controller/driver users manual u10105ej4v1um00 18.3 lcd controller/driver control registers the lcd controller/driver is controlled by the following two registers. ? lcd display mode register (lcdm) ? lcd display control register (lcdc) (1) lcd display mode register (lcdm) this register sets display operation enabling/ disabling, the lcd clock, frame frequency, and display mode selection. lcdm is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets lcdm to 00h. figure 18-3. lcd display mode register format lcdm2 lcdm1 lcdm0 number of time divisions bias method 0 0 0 4 1/3 0 0 1 3 1/3 0 1 0 2 1/2 0 1 1 3 1/2 1 0 0 static other than above setting prohibited lcdm5 lcdm5 lcdm4 lcd clock selection (see note ) f xx = 5.0 mhz f xx = 4.19 mhz f xt = 32.768 khz 000f w /2 9 (76 hz) f w /2 9 (64 hz) f w /2 9 (64 hz) 001f w /2 8 (153 hz) f w /2 8 (128 hz) f w /2 8 (128 hz) 010f w /2 7 (305 hz) f w /2 7 (256 hz) f w /2 7 (256 hz) 011f w /2 6 (610 hz) f w /2 6 (512 hz) f w /2 6 (512 hz) lcdon lcd display 0 display on (all segment outputs signal non-selection.) 1 display off note the lcd clock is supplied from the clock timer. when lcd display is performed, 1 should be set in bit 1 (tmc21) of the clock timer mode control register (tmc2). if tmc21 is reset to 0 during lcd display, the lcd clock supply will be stopped and the display will be disrupted. remarks 1. f w : clock timer clock frequency (f xx /2 7 or f xt ) 2. f xx : main system clock frequency (f x or f x /2) 3. f x : main system clock oscillation frequency 4. f xt : subsystem clock oscillation frequency symbol lcdm lcdon 6 lcdm6 5 lcdm5 4 lcdm4 3 0 2 lcdm2 1 lcdm1 0 lcdm0 address ffb0h state after reset 00h r/w r/w 7
375 chapter 18 lcd controller/driver users manual u10105ej4v1um00 table 18-3. frame frequencies (hz) lcdcl f w /2 9 f w /2 8 f w /2 7 f w /2 6 duty (64 hz) (128 hz) (256 hz) (512 hz) static 64 128 256 512 1/2 32 64 128 256 1/3 21 43 85 171 1/4 16 32 64 128 remarks 1. figures in parentheses apply to operation with f x = 4.19 mhz or f xt = 32.768 khz. 2. f w : clock timer clock frequency (f xx /2 7 or f xt ) 3. f xx : main system clock frequency (f x or f x /2) 4. f x : main system clock oscillation frequency 5. f xt : subsystem clock oscillation frequency
376 chapter 18 lcd controller/driver users manual u10105ej4v1um00 (2) lcd display control register (lcdc) this register sets cut-off of the current flowing to split resistors for lcd drive voltage generation and switchover between segment output and input/output port functions. lcdc is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets lcdc to 00h. figure 18-4. lcd display control register format cautions 1. pins which perform segment output cannot be used as output port pins even if 0 is set in the port register. 2. if a pin which performs segment output is read as a port, its value will be 0. 3. pins set as segment outputs by lcdc cannot have an internal pull-up resistor connected regardless of the value of bits 0 and 1 (puo8 and puo9) of pull-up resistor option register h. symbol lcdc 7 lcdc7 6 lcdc6 5 lcdc5 4 lcdc4 3 0 2 0 1 leps lips address ffb2h state after reset 00h r/w r/w leps lips lcd driving power supply selection 0 0 does not supply power to lcd. 0 1 supplies power to lcd from v dd pin. 1 0 supplies power to lcd from bias pin. (shorts bias and v lc0 pins internally.) 1 1 setting prohibited lcdc7 lcdc6 lcdc5 lcdc4 p80/s39-p97/s24 pin functions port pins segment pins p80-p97 none 0000 p80-p95 s24, s25 0001 p80-p93 s24-s27 0010 p80-p91 s24-s29 0011 p80-p87 s24-s31 0100 p80-p85 s24-s33 0101 p80-p83 s24-s35 0110 p80-p81 s24-s37 0111 none s24-s39 1000 other than above setting prohibited 0
377 chapter 18 lcd controller/driver users manual u10105ej4v1um00 18.4 lcd controller/driver settings lcd controller/driver settings should be performed as shown below. when the lcd controller/driver is used, the clock timer should be set to the operational state beforehand. <1>set watch operation enabled in timer clock selection register 2 (tcl2) and the clock timer mode control register (tmc2). <2>set the initial value in the display data memory (fa58h to fa7fh). <3>set the pins to be used as segment outputs in the lcd display control register (lcdc). <4>set the display mode and lcd clock in the lcd display mode register (lcdm). next, set data in the display data memory according to the display contents.
378 chapter 18 lcd controller/driver users manual u10105ej4v1um00 18.5 lcd display data memory the lcd display data memory is mapped onto addresses fa58h to fa7fh. the data stored in the lcd display data memory can be displayed on an lcd panel by the lcd controller/driver. figure 18-5 shows the relationship between the lcd display data memory contents and the segment outputs/ common outputs. any area not used for display can be used as normal ram. figure 18-5. relationship between lcd display data memory contents and segment/common outputs caution the higher 4 bits of the lcd display data memory do not incorporate memory. be sure to set them to 0. s0 fa7fh s1 fa7eh s2 fa7dh s3 fa7ch s37/p82 fa5ah s38/p81 fa59h s39/p80 fa58h com3 com2 com1 com0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 address
379 chapter 18 lcd controller/driver users manual u10105ej4v1um00 18.6 common signals and segment signals an individual pixel on an lcd panel lights when the potential difference of the corresponding common signal and segment signal reaches or exceeds a given voltage (the lcd drive voltage v lcd ). as an lcd panel deteriorates if a dc voltage is applied in the common signals and segment signals, it is driven by ac voltage. (1) common signals for common signals, the selection timing order is as shown in table 18-4 according to the number of time divisions set, and operations are repeated with these as the cycle. in the static mode, the same signal is output to com0 through com3. with 2-time-division operation, pins com2 and com3 are left open, and with 3-time-division operation, the com3 pin is left open. table 18-4. com signals (2) segment signals segment signals correspond to a 40-byte lcd display data memory (fa58h to fa7fh). each display data memory bit 0, bit 1, bit 2, and bit 3 is read in synchronization with the com0, com1, com2 and com3 timings respectively, and if the value of the bit is 1, it is converted to the selection voltage. if the value of the bit is 0, it is converted to the non-selection voltage and output to a segment pin (s0 to s39) (s24 to s39 have a dual function as input/output port pins). consequently, it is necessary to check what combination of front surface electrodes (corresponding to the segment signals) and rear surface electrodes (corresponding to the common signals) of the lcd display to be used form the display pattern, and then write bit data corresponding on a one-to-one basis with the pattern to be displayed. in addition, because lcd display data memory bits 1 and 2 are not used with the static method, bits 2 and 3 are not used with the 2-time-division method, and bit 3 is not used with the 3-time-division method, these can be used for other than display purposes. bits 4 to 7 are fixed at 0. com signal time division static 2-time division 3-time division 4-time division open open open com0 com1 com2 com3
380 chapter 18 lcd controller/driver users manual u10105ej4v1um00 (3) common signal and segment signal output waveforms the voltages shown in table 18-5 are output in the common signals and segment signals. the v lcd on voltage is only produced when the common signal and segment signal are both at the selection voltage; other combinations produce the off voltage. table 18-5. lcd drive voltages (a) static display mode segment select non-select common v ss , v lc0 v lc0 , v ss v lc0 , v ss Cv lcd , +v lcd 0 v , 0 v (b) 1/2 bias method segment select non-select common v ss , v lc0 v lc0 , v ss select level v lc0 , v ss Cv lcd , +v lcd 0 v , 0 v non-select level v lc1 =v lc2 C1/2v lcd , +1/2v lcd +1/2v lcd , C1/2v lcd (c) 1/3 bias method segment select non-select common v ss , v lc0 v lc1 , v lc2 select level v lc0 , v ss Cv lcd , +v lcd C1/3v lcd , +1/3v lcd non-select level v lc2 , v lc1 C1/3v lcd , +1/3v lcd C1/3v lcd , +1/3v lcd
381 chapter 18 lcd controller/driver users manual u10105ej4v1um00 figure 18-6 shows the common signal waveform, and figure 18-7 shows the common signal and segment signal voltages and phases. figure 18-6. common signal waveform (a) static display mode remarks 1. t : one lcdcl cycle 2. t f : frame frequency (b) 1/2 bias method remarks 1. t : one lcdcl cycle 2. t f : frame frequency (c) 1/3 bias method remarks 1. t : one lcdcl cycle 2. t f : frame frequency comn (static) t f = t v lc0 v ss v lcd comn (divided by 2) t f = 2 x t v lc0 v ss v lcd v lc2 comn (divided by 3) t f = 3 x t v lc0 v ss v lcd v lc2 comn (divided by 3) t f = 3 x t v lc0 v ss v lcd v lc1 v lc2 t f = 4 x t comn (divided by 4) v lc0 v ss v lcd v lc1 v lc2
382 chapter 18 lcd controller/driver users manual u10105ej4v1um00 figure 18-7. common signal and static signal voltages and phases (a) static display mode remark t : one lcdcl cycle (b) 1/2 bias method remark t : one lcdcl cycle (c) 1/3 bias method remark t : one lcdcl cycle selected not selected common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt selected not selected common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt v lc2 v lc2 selected not selected common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt v lc2 v lc2 v lc1 v lc1
383 chapter 18 lcd controller/driver users manual u10105ej4v1um00 18.7 supply of lcd drive voltages v lc0 , v lc1 , v lc2 split resistors for producing the lcd drive voltages can be incorporated in the m pd78062, 78063, 78064, 78062y, 78063y, and 78064y by mask option (the m pd78p064, 78p064y do not incorporate split resistors). incorporating the split resistors makes it possible to produce lcd drive voltages appropriate to the various bias methods shown in table 18-6 without using external split resistors. also, an lcd drive voltage can be externally supplied from the bias pin to produce other lcd drive voltages. table 18-6. lcd drive voltages (with on-chip split resistor) bias method no bias 1/2 1/3 lcd (static mode) bias bias drive voltage v lc0 v lcd v lcd v lcd v lc1 2/3v lcd 1/2v lcd note 2/3v lcd v lc2 1/3v lcd 1/3v lcd note with the 1/2 bias method, the v lc1 pin and v lc2 pin must be connected externally. remarks 1. when the bias pin and v lc0 pin are open, v lcd = 3/5v dd (with on- chip split resistor). 2. when the bias pin and v lc0 pin are connected, v lcd = v dd . examples of internal supply of the lcd drive voltage in accordance with table 18-6 are shown in figures 18- 8 and 18-9. an example of supply of the lcd drive voltage from off-chip is shown in figure 18-10. stepless lcd drive voltages can be supplied by means of variable resistor r.
384 chapter 18 lcd controller/driver users manual u10105ej4v1um00 figure 18-8. lcd drive power supply connection examples (with on-chip split resistor) (a) 1/3 bias method and static display mode (b) 1/2 bias method mode (example with v dd = 5 v, v lcd = 3 v) (example with v dd = 5 v, v lcd = 5 v) (c) 1/3 bias method and static display mode (example with v dd = 5 v, v lcd = 5 v) 2r leps (= 0) lips v dd bias pin r r r v lc0 v lc1 v lc2 v ss v lcd v lcd = 3/5v dd p-ch p-ch 2r leps (= 0) lips v dd bias pin r r r v lc0 v lc1 v lc2 v ss v lcd v lcd = v dd p-ch p-ch p-ch 2r leps (= 0) lips v dd bias pin r r r v lc0 v lc1 v lc2 v ss v lcd v lcd = v dd p-ch
385 chapter 18 lcd controller/driver users manual u10105ej4v1um00 figure 18-9. lcd drive power supply connection examples (with external split resistor) (a) static display mode note (b) static display mode (example with v dd = 5 v, v lcd = 5 v) (example with v dd = 5 v, v lcd = 3 v) note lips should always be set to 1 (including in standby mode). (c) 1/2 bias method (d) 1/3 bias method (example with v dd = 5 v, v lcd = 3 v) (example with v dd = 5 v, v lcd = 3 v) p-ch leps (= 0) lips v dd bias pin v lc0 v lc1 v lc2 v ss v lcd v lcd = v dd p-ch p-ch leps (= 0) lips v dd bias pin v lc0 v lc1 v lc2 v ss v lcd v lcd = 3/5v dd p-ch 2r 3r p-ch leps (= 0) lips v dd bias pin v lc0 v lc1 v lc2 v ss v lcd v lcd = 3/5v dd p-ch 4r 3r 3r p-ch leps (= 0) lips v dd bias pin v lc0 v lc1 v lc2 v ss v lcd v lcd = 3/5v dd p-ch 2r r r r
386 chapter 18 lcd controller/driver users manual u10105ej4v1um00 figure 18-10. example of lcd drive voltage supply from off-chip p-ch leps lips (= 0) v dd bias pin r r r v lc0 v lc1 v lc2 v ss v lcd v lcd =v dd p-ch v dd 3r + r 3r r
387 chapter 18 lcd controller/driver users manual u10105ej4v1um00 18.8 display modes 18.8.1 static display example figure 18-12 shows the connection of a static type 5-digit lcd panel with the display pattern shown in figure 18-11 with the m pd78064 subseries segment (s0 to s39) and common (com0) signals. the display example is 123.45, and the display data memory contents (addresses fa58h to fa7fh) correspond to this. an explanation is given here taking the example of the third digit 3. ( ). in accordance with the display pattern in figure 18-11, selection and non-selection voltages must be output to pins s16 through s23 as shown in table 18-7 at the com0 common signal timing. table 18-7. selection and non-selection voltages (com0) segment s16 s17 s18 s19 s20 s21 s22 s23 common com0 ssssnssnss s: selection, ns: non-selection from this, it can be seen that 10101111 must be prepared in the bit0 bits of the display data memory (addresses fa68h to fa6fh) corresponding to s16 to s23. the lcd drive waveforms for s19, s20, and com0 are shown in figure 18-13. when s19 is at the selection voltage at the timing for selection with com0, it can be seen that the +v lcd /Cv lcd ac square wave, which is the lcd illumination (on) level, is generated. shorting the com0 through com3 lines increases the current drive capability because the same waveform as com0 is output to com1 through com3. figure 18-11. static lcd display pattern and electrode connections remark n = 0 to 4 s 8n+3 s 8n+2 s 8n+5 s 8n+1 s 8n s 8n+4 s 8n+6 s 8n+7 com0
388 chapter 18 lcd controller/driver users manual u10105ej4v1um00 figure 18-12. static lcd panel connection example timing strobes com3 com2 com1 com0 bit0 bit1 bit2 bit3 s0 s1 s2 s3 0 x fa7fh 1 e 0 d 1 c s4 s5 s6 s7 1 b 1 a 0 9 1 8 s8 s9 s10 s11 0 7 1 6 1 5 0 4 s12 s13 s14 s15 1 3 1 2 0 1 0 0 s16 s17 s18 s19 1 fa6fh 1 e 1 d 1 c s20 s21 s22 s23 0 b 1 a 0 9 1 8 s24 s25 s26 s27 0 7 0 6 1 5 1 4 s28 s29 s30 s31 0 3 0 2 1 1 1 0 s32 s33 s34 s35 0 fa5fh 1 e 1 d 0 c s36 s37 s38 s39 0 b 0 a 0 9 0 fa58h can be shorted. data memory addresses lcd panel x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
389 chapter 18 lcd controller/driver users manual u10105ej4v1um00 figure 18-13. static lcd drive waveform examples t f v lc0 v ss com0 v lc0 v ss s19 v lc0 v ss s20 +v lcd 0 com0-s20 ? lcd +v lcd 0 com0-s19 ? lcd
390 chapter 18 lcd controller/driver users manual u10105ej4v1um00 18.8.2 2-time-division display example figure 18-15 shows the connection of a 2-time-division type 10-digit lcd panel with the display pattern shown in figure 18-14 with the m pd78064, 78064y subseries segment signals (s0 to s39) and common signals (com0, com1). the display example is 123456.7890, and the display data memory contents (addresses fa58h to fa7fh) correspond to this. an explanation is given here taking the example of the eighth digit 3 ( ). in accordance with the display pattern in figure 18-14, selection and non-selection voltages must be output to pins s28 through s31 as shown in table 18-8 at the com0 and com1 common signal timings. table 18-8. selection and non-selection voltages (com0, com1) segment s28 s29 s30 s31 common com0 s s ns ns com1 ns s s s s: selection, ns: non-selection from this, it can be seen that, for example, xx10 must be prepared in the display data memory (address fa80h) corresponding to s31. examples of the lcd drive waveforms between s31 and the common signals are shown in figure 18-16. when s31 is at the selection voltage at the com1 selection timing, it can be seen that the +v lcd /Cv lcd ac square wave, which is the lcd illumination (on) level, is generated. figure 18-14. 2-time-division lcd display pattern and electrode connections remark n = 0 to 9 s 4n + 2 s 4n + 3 s 4n + 1 s 4n com0 com1
391 chapter 18 lcd controller/driver users manual u10105ej4v1um00 figure 18-15. 2-time-division lcd panel connection example remark in bits marked x, 0 or 1 may be stored because this is a 2-time-division display. timing strobes com3 com2 com1 com0 bit0 bit1 bit2 bit3 s0 s1 s2 s3 1 fa7fh 1 e 1 d 1 c s4 s5 s6 s7 1 b 1 a 1 9 0 8 s8 s9 s10 s11 1 7 1 6 1 5 1 4 s12 s13 s14 s15 1 3 1 2 1 1 0 0 s16 s17 s18 s19 1 fa6fh 0 e 1 d 1 c s20 s21 s22 s23 1 b 0 a 1 9 0 8 s24 s25 s26 s27 1 7 1 6 1 5 0 4 s28 s29 s30 s31 1 3 1 2 0 1 0 0 s32 s33 s34 s35 0 fa5fh 1 e 0 d 1 c s36 s37 s38 s39 1 b 1 a 0 9 0 fa58h open data memory addresses lcd panel open 0 0 1 1 0 1 1 0 0 1 1 1 0 0 1 0 1 1 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 1 1 0 0 0 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
392 chapter 18 lcd controller/driver users manual u10105ej4v1um00 figure 18-16. 2-time-division lcd drive waveform examples (1/2 bias method) t f v lc0 v ss com0 v lc0 v ss v lc0 v ss s31 +v lcd 0 com1-s31 ? lcd v lcd 0 com0-s31 ? lcd v lc1 (v lc2 ) com1 +1/2v lcd +1/2v lcd ?/2v lcd ?/2v lcd v lc1 (v lc2 ) v lc1 (v lc2 )
393 chapter 18 lcd controller/driver users manual u10105ej4v1um00 18.8.3 3-time-division display example figure 18-18 shows the connection of a 3-time-division type 13-digit lcd panel with the display pattern shown in figure 18-17 with the m pd78064, 78064y subseries segment signals (s0 to s38) and common signals (com0 to com2). the display example is 123456.7890123, and the display data memory contents (addresses fa59h to fa7fh) correspond to this. an explanation is given here taking the example of the eighth digit 6. ( ). in accordance with the display pattern in figure 18-17, selection and non-selection voltages must be output to pins s21 through s23 as shown in table 18-9 at the com0 to com2 common signal timings. table 18-9. selection and non-selection voltages (com0 to com2) segment s21 s22 s23 common com0 ns s s com1 s s s com2 s s s: selection, ns: non-selection from this, it can be seen that x110 must be prepared in the display data memory (address fa6ah) corresponding to s21. examples of the lcd drive waveforms between s21 and the common signals are shown in figure 18-19 (1/2 bias method) and figure 18-20 (1/3 bias method). when s21 is at the selection voltage at the com1 selection timing, and s21 is at the selection voltage at the com2 selection timing, it can be seen that the +v lcd /Cv lcd ac square wave, which is the lcd illumination (on) level, is generated. figure 18-17. 3-time-division lcd display pattern and electrode connections remark n = 0 to 12 s 3n + 2 s 3n com0 com2 s 3n + 1 com1
394 chapter 18 lcd controller/driver users manual u10105ej4v1um00 figure 18-18. 3-time-division lcd panel connection example remarks 1. x : irrelevant bits because they have no corresponding segment in the lcd panel 2. x : irrelevant bits because this is a 3-time-division display timing strobes com3 com2 com1 com0 bit0 bit1 bit2 bit3 s0 s1 s2 s3 1 0 fa7fh 1 1 e 0 d 1 0 c s4 s5 s6 s7 1 1 b 0 a 1 0 9 0 0 8 s8 s9 s10 s11 0 7 1 0 6 1 1 5 1 4 s12 s13 s14 s15 1 0 3 1 0 2 1 1 1 0 0 s16 s17 s18 s19 1 1 fa6fh 1 e 1 0 d 1 0 c s20 s21 s22 s23 1 b 0 1 a 1 1 9 1 8 s24 s25 s26 s27 0 0 7 1 1 6 1 5 1 0 4 s28 s29 s30 s31 0 0 3 1 2 1 0 1 1 1 0 s32 s33 s34 s35 0 fa5fh 1 0 e 1 1 d 0 c s36 s37 s38 1 0 b 0 0 a 0 9 fa58h data memory addresses lcd panel open 1 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x' x' x' x' x' x' x' x' x' x' x' x' x'
395 chapter 18 lcd controller/driver users manual u10105ej4v1um00 figure 18-19. 3-time-division lcd drive waveform examples (1/2 bias method) t f v lc0 v ss com0 v lc0 v ss v lc0 v ss com2 +v lcd 0 com1-s21 ? lcd +v lcd 0 com0-s21 ? lcd com1 +1/2v lcd +1/2v lcd ?/2v lcd ?/2v lcd v lc0 v ss s21 +v lcd 0 com2-s21 ? lcd +1/2v lcd ?/2v lcd v lc1 (v lc2 ) v lc1 (v lc2 ) v lc1 (v lc2 ) v lc1 (v lc2 )
396 chapter 18 lcd controller/driver users manual u10105ej4v1um00 figure 18-20. 3-time-division lcd drive waveform examples (1/3 bias method) v lc0 v lc2 com0 +v lcd 0 com0-s21 ? lcd v lc1 +1/3v lcd ?/3v lcd v ss v lc0 v lc2 com1 v lc1 v ss v lc0 v lc2 com2 v lc1 v ss v lc0 v lc2 s21 v lc1 v ss +v lcd 0 com1-s21 ? lcd +1/3v lcd ?/3v lcd +v lcd 0 com2-s21 ? lcd +1/3v lcd ?/3v lcd t f
397 chapter 18 lcd controller/driver users manual u10105ej4v1um00 18.8.4 4-time-division display example figure 18-22 shows the connection of a 4-time-division type 20-digit lcd panel with the display pattern shown in figure 18-21 with the m pd78064, 78064y subseries segment signals (s0 to s39) and common signals (com0 to com3). the display example is 123456.78901234567890, and the display data memory contents (addresses fa58h to fa7fh) correspond to this. an explanation is given here taking the example of the 15th digit 6. ( ). in accordance with the display pattern in figure 18-21, selection and non-selection voltages must be output to pins s28 and s29 as shown in table 18- 10 at the com0 to com3 common signal timings. table 18-10. selection and non-selection voltages (com0 to com3) segment s28 s29 common com0 s s com1 ns s com2 s s com3 s s s: selection, ns: non-selection from this, it can be seen that 1101 must be prepared in the display data memory (address fa63h) corresponding to s28. examples of the lcd drive waveforms between s28 and the com0 and com1 signals are shown in figure 18- 23 (for the sake of simplicity, waveforms for com2 and com3 have been omitted). when s28 is at the selection voltage at the com0 selection timing, it can be seen that the +v lcd /Cv lcd ac square wave, which is the lcd illumination (on) level, is generated. figure 18-21. 4-time-division lcd display pattern and electrode connections remark n = 0 to 18 com0 s 2n com1 s 2n + 1 com2 com3
398 chapter 18 lcd controller/driver users manual u10105ej4v1um00 figure 18-22. 4-time-division lcd panel connection example timing strobes com3 com2 com1 com0 bit0 bit1 bit2 bit3 s0 s1 s2 s3 1 1 0 fa7fh 1 1 1 e 1 1 0 d 1 0 0 c s4 s5 s6 s7 1 1 0 b 1 1 1 a 1 1 0 9 1 0 0 8 s8 s9 s10 s11 1 1 0 7 1 1 1 6 1 1 0 5 1 0 1 4 s12 s13 s14 s15 0 1 0 3 1 0 0 2 1 1 0 1 0 0 1 0 s16 s17 s18 s19 1 0 0 fa6fh 0 1 1 e 0 1 0 d 0 0 0 c s20 s21 s22 s23 1 1 0 b 1 1 1 a 1 1 0 9 1 0 0 8 s24 s25 s26 s27 1 1 0 7 1 1 1 6 1 1 0 5 1 0 0 4 s28 s29 s30 s31 1 1 1 3 1 1 1 2 1 1 0 1 1 0 1 0 s32 s33 s34 s35 0 1 0 fa5fh 1 0 0 e 1 1 0 d 0 0 1 c s36 s37 s38 s39 1 0 0 b 0 1 1 a 0 1 0 9 0 0 0 fa58h data memory addresses lcd panel 1 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 0
399 chapter 18 lcd controller/driver users manual u10105ej4v1um00 figure 18-23. 4-time-division lcd drive waveform examples (1/3 bias method) t f v lc0 v lc2 com0 +v lcd 0 com0-s28 ? lcd v lc1 +1/3v lcd ?/3v lcd v ss v lc0 v lc2 com1 v lc1 v ss v lc0 v lc2 com2 v lc1 v ss v lc0 v lc2 com3 v lc1 v ss +v lcd 0 com1-s28 ? lcd +1/3v lcd ?/3v lcd v lc0 v lc2 s28 v lc1 v ss
400 users manual u10105ej4v1um00 [memo]
401 users manual u10105ej4v1um00 chapter 19 interrupt and test functions 19.1 interrupt function types the following three types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally (that is, even in interrupt disabled state). it does not undergo interrupt priority control and is given top priority over all other interrupt requests. it generates a standby release signal. one interrupt from the watchdog timer is incorporated as a non-maskable interrupt. (2) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register (pr). multiple high priority interrupts can be applied to low priority interrupts. if two or more interrupts with the same priority are simultaneously generated, each interrupts has a predetermined priority (see table 19-1 ). a standby release signal is generated. six external interrupts and 12 internal interrupts are incorporated as maskable interrupts. (3) software interrupt this is a vectored interrupt to be generated by executing the brk instruction. it is acknowledged even in interrupt disabled state. the software interrupt does not undergo interrupt priority control.
402 chapter 19 interrupt and test functions users manual u10105ej4v1um00 19.2 interrupt sources and configuration twenty non-maskable, maskable, and software interrupts are provided as interrupt causes (see table 19-1 ). table 19-1. interrupt source list maskability default( note1 ) interrupt source internal/ vector type priority name trigger external address ( note2 ) non- intwdt watchdog timer overflow (with internal 0004h (a) maskable watchdog timer mode 1 selected) maskable 0 intwdt watchdog timer overflow (with (b) interval timer mode selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h (d) 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 0010h 7 intcsi0 end of serial interface channel 0 internal 0014h (b) transfer 8 intser serial interface channel 2 uart reception 0018h error generation 9 intsr end of serial interface channel 2 001ah uart reception intcsi2 end of serial interface channel 2 3-wire transfer 10 intst end of serial interface channel 2 001ch uart transfer 11 inttm3 reference time interval signal from 001eh watch timer 12 inttm00 generation of 16-bit timer register, 0020h capture/compare register (cr00) match signal 13 inttm01 generation of 16-bit timer register, 0022h capture/compare register (cr01) match signal 14 inttm1 generation of 8-bit timer/event 0024h counter 1 match signal 15 inttm2 generation of 8 bit timer/event 0026h counter 2 match signal 16 intad end of a/d converter conversion 0028h software brk brk instruction execution internal 003eh (e) notes 1. default priorities are intended for two or more simultaneously generated maskable interrupts. 0 is the highest priority and 16 is the lowest priority. 2. basic configuration types (a) to (e) correspond to (a) to (e) of figure 19-1.
403 chapter 19 interrupt and test functions users manual u10105ej4v1um00 figure 19-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0) internal bus priority control circuit vector table address generator standby release signal interrupt request internal bus ie pr isp mk if interrupt request priority control circuit vector table address generator standby release signal internal bus ie pr isp mk if priority control circuit vector table address generator standby release signal interrupt request sampling clock edge detector sampling clock select register (scs) external interrupt mode register (intm0)
404 chapter 19 interrupt and test functions users manual u10105ej4v1um00 figure 19-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (except intp0) if : interrupt request flag ie : interrupt enable flag isp : inservice priority flag mk : interrupt mask flag pr : priority specify flag (e) software interrupt external interrupt mode register (intm0, intm1) edge detector interrupt request ie pr isp mk if priority control circuit vector table address generator standby release signal internal bus internal bus priority control circuit vector table address generator interrupt request
405 chapter 19 interrupt and test functions users manual u10105ej4v1um00 19.3 interrupt function control registers the following six types of registers are used to control the interrupt functions. ? interrupt request flag register (if0l, if0h, if1l) ? interrupt mask flag register (mk0l, mk0h, mk1l) ? priority specify flag register (pr0l, pr0h, pr1l) ? external interrupt mode register (intm0, intm1) ? sampling clock select register (scs) ? program status word (psw) table 19-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specify flags corresponding to interrupt request sources. table 19-2. various flags corresponding to interrupt request sources interrupt request signal name interrupt request flag interrupt mask flag priority specify flag intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intp4 pif4 pmk4 ppr4 intp5 pif5 pmk5 ppr5 inttm00 tmif00 tmmk00 tmpr00 inttm01 tmif01 tmmk01 tmpr01 inttm1 tmif1 tmmk1 tmpr1 inttm2 tmif2 tmmk2 tmpr2 inttm3 tmif3 tmmk3 tmpr3 intwdt tmif4 tmmk4 tmpr4 intcsi0 csiif0 csimk0 csipr0 intsr/intcsi2 srif srmk srpr intser serif sermk serpr intst stif stmk stpr intad adif admk adpr
406 chapter 19 interrupt and test functions users manual u10105ej4v1um00 (1) interrupt request flag registers (if0l, if0h, if1l) the interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. it is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input. if0l, if0h, and if1l are set with a 1-bit or 8-bit memory manipulation instruction. if if0l and if0h are used as a 16-bit register if0 use a 16-bit memory manipulation instruction for the setting. reset input sets these registers to 00h. figure 19-2. interrupt request flag register format note wtif is test input flag. vectored interrupt is not generated. cautions 1. tmif4 flag is r/w enabled only when a watchdog timer is used as an interval timer. if a watchdog timer is used in watchdog timer mode 1, set tmif4 flag to 0. 2. because port 0 has a dual function as the external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, 1 should be set in the interrupt mask flag before using the output mode. 3. set always 0 in if1l bits 3 through 6, if0l bit 7, and if0h bit 1. 7 0 symbol if0l 6 pif5 5 pif4 4 pif3 3 pif2 2 pif1 1 pif0 0 tmif4 address ffe0h 00h after reset r/w r/w if 0 1 interrupt request flag no interrupt request signal interrupt request signal is generated; interrupt request state 7 tmif01 if0h 6 tmif00 5 tmif3 4 stif 3 srif 2 serif 1 0 0 csiif0 7 wtif note if1l 6 0 5 0 4 0 3 0 2 adif 1 tmif2 0 tmif1 ffe1h 00h r/w ffe2h 00h r/w
407 chapter 19 interrupt and test functions users manual u10105ej4v1um00 (2) interrupt mask flag registers (mk0l, mk0h, mk1l) the interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. mk0l, mk0h, and mk1l are set with a 1-bit or 8-bit memory manipulation instruction. if mk0l and mk0h are used as a 16-bit register mk0, use a 16-bit memory manipulation instruction for the setting. reset input sets these registers to ffh. figure 19-3. interrupt mask flag register format note wtmk controls standby mode release enable/disable. cautions 1. if tmmk4 flag is read when a watchdog timer is used in watchdog timer mode 1, mk0 value becomes undefined. 2. because port 0 has a dual function as the external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, 1 should be set in the interrupt mask flag before using the output mode. 3. set always 1 in mk1l bits 3 through 6, mk0l bit 7, and mk0h bit 1. 7 1 symbol mk0l 6 pmk5 5 pmk4 4 pmk3 3 pmk2 2 pmk 1 pmk 0 address ffe4h ffh after reset r/w r/w xxmkx 0 1 interrupt servicing control interrupt servicing enabled interrupt servicing disabled 7 mk0h 654 stmk 3 srmk 21 1 0 7 wtmk note mk1l 6 1 5 1 4 1 3 1 210 ffe5h ffh r/w ffe6h ffh r/w admk tmmk2 tmmk1 csimk0 sermk tmmk3 tmmk00 tmmk01 tmmk4
408 chapter 19 interrupt and test functions users manual u10105ej4v1um00 (3) priority specify flag registers (pr0l, pr0h, and pr1l) the priority specify flag is used to set the corresponding maskable interrupt priority orders. pr0l, pr0h, and pr1l are set with a 1-bit or 8-bit memory manipulation instruction. if pr0l and pr0h are used as a 16-bit register pr0, use a 16-bit memory manipulation instruction for the setting. reset input sets these registers to ffh. figure 19-4. priority specify flag register format cautions 1. when a watchdog timer is used in watchdog timer mode 1, set 1 in tmpr4 flag. 2. set always 1 in pr1l bits 3 through 7, pr0l bit 7, and pr0h bit 1. 7 1 symbol pr0l 6 ppr5 5 ppr4 4 ppr3 3 ppr2 2 ppr1 1 ppr0 0 address ffe8h ffh after reset r/w r/w 0 1 priority level selection high priority level low priority level 7 pr0h 654 stpr 3 srpr 21 1 0 7 1 pr1l 6 1 5 1 4 1 3 1 2 adpr 10 ffe9h ffh r/w ffeah ffh r/w xxprx tmpr1 tmpr2 serpr tmpr4 tmpr01 tmpr00 tmpr3 csipr0
409 chapter 19 interrupt and test functions users manual u10105ej4v1um00 (4) external interrupt mode register (intm0, intm1) these registers set the valid edge for intp0 to intp5. intm0 and intm1 are set by 8-bit memory manipulation instructions. reset input sets these registers to 00h. figure 19-5. external interrupt mode register 0 format address ffech 00h after reset r/w r/w 0 0 1 1 intp0 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es11 7 es31 symbol intm0 6 es30 5 es21 4 es20 3 es11 2 es10 1 0 0 0 0 1 0 1 es10 0 0 1 1 intp1 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es21 0 1 0 1 es20 0 0 1 1 intp2 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es31 0 1 0 1 es30
410 chapter 19 interrupt and test functions users manual u10105ej4v1um00 figure 19-6. external interrupt mode register 1 format address ffedh 00h after reset r/w r/w 0 0 1 1 intp3 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es41 7 0 symbol intm1 6 0 5 es61 4 es60 3 es51 2 es50 1 es41 0 es40 0 1 0 1 es40 0 0 1 1 intp4 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es51 0 1 0 1 es50 0 0 1 1 intp5 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es61 0 1 0 1 es60
411 chapter 19 interrupt and test functions users manual u10105ej4v1um00 (5) sampling clock select register (scs) this register is used to set the valid edge clock sampling clock to be input to intp0. when remote controlled data reception is carried out using intp0, digital noise is removed with sampling clocks. scs is set with an 8-bit memory manipulation instruction. reset input sets scs to 00h. figure 19-7. sampling clock select register format caution f xx /2 n is a clock to be supplied to the cpu and f xx /2 5 , f xx /2 6 and f xx /2 7 are clocks to be supplied to the peripheral hardware. f xx /2 n stops in the halt mode. remarks 1. n : value (n=0 to 4) at bits 0 to 2 (pcc0 to pcc2) of processor clock control register 2. f xx : main system clock frequency (f x or f x /2) 3. f x : main system clock oscillation frequency 4. mcs : oscillation mode selection register bit 0 5. values in parentheses when operated with f x = 5.0 mhz. address ff47h 00h after reset r/w r/w 0 0 1 1 intp0 sampling clock selection f xx /2 n f xx /2 7 f xx /2 5 f xx /2 6 scs1 7 0 symbol scs 6 0 5 0 4 0 3 0 2 0 1 scs1 0 scs0 0 1 0 1 scs0 mcs = 1 mcs = 0 f x /2 7 (39.1 khz) f x /2 5 (156.3 khz) f x /2 6 (78.1 khz) f x /2 8 (19.5 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz)
412 chapter 19 interrupt and test functions users manual u10105ej4v1um00 when the intp0 input level is active twice in succession, the noise remover sets pif0 flag to 1. figure 19-8. noise remover input/output timing (during rising edge detection) (a) when input is less than the sampling cycle (t smp ) (b) when input is equal to or twice the sampling cycle (t smp ) (c) when input is twice or more than the cycle frequency (t smp ) t smp sampling clock intp0 pif0 "l" because intp0 level is not active twice in succession, pif0 out p ut remains at low level. t smp sampling clock intp0 pif0 because intp0 level is active twice in succession in 2 , pif0 flag is set to 1. 1 2 2 t smp sampling clock intp0 pif0 because intp0 level is active two or more times in succession, pif0 flag is set to 1.
413 chapter 19 interrupt and test functions users manual u10105ej4v1um00 (6) program status word (psw) the program status word is a register to hold the instruction execution result and the current status for interrupt request. the ie flag to set maskable interrupt enable/disable and the isp flag to control multiple interrupt servicing are mapped. besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (ei and di). when a vectored interrupt is acknowledged or the brk instruction is executed, psw is automatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt is acknowledged contents of the priority specify flag of the acknowledged interrupt are transferred to the isp flag. the acknowledged interrupt is also saved into the stack with the push psw instruction. it is reset from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 19-9. program status word format 7 ie psw 6 z 5 rbs1 4 ac 3 rbs0 2 0 1 isp 0 cy 02h state after reset isp 0 used when normal instruction is executed priority of interrupt currently being received high-priority interrupt servicing (low-priority interrupt disable) 1 interrupt not acknowledged or low-priority interrupt servicing (all-maskable interrupts enable) ie interrupt acknowledge enable/disable 0 disable 1 enable
414 chapter 19 interrupt and test functions users manual u10105ej4v1um00 19.4 interrupt servicing operations 19.4.1 non-maskable interrupt acknowledge operation a non-maskable interrupt is unconditionally acknowledged even if in an interrupt acknowledge disable state. it does not undergo interrupt priority control and has highest priority over all other interrupts. if a non-maskable interrupt request is acknowledged, the acknowledged interrupt is saved in the stacks, psw and pc, in that order, the ie and isp flags are reset to 0, and the vector table contents are loaded into pc and branched. a new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following reti instruction execution) and one main routine instruction is executed. if a new non-maskable interrupt request is generated twice or more during non-maskable interrupt service program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt service program execution.
415 chapter 19 interrupt and test functions users manual u10105ej4v1um00 figure 19-10. non-maskable interrupt acknowledge flowchart wdtm : watchdog timer mode register wdt : watchdog timer figure 19-11. non-maskable interrupt acknowledge timing instruction instruction cpu instruction tmif4 psw and pc save, jump to interrupt servicing interrupt sevicing program wdtm4=1 (with watchdog timer mode selected)? overflow in wdt? wdtm3=0 (with non-maskable interrupt selected)? interrupt request generation wdt interrupt servicing? interrupt control register unaccessed? interrupt service start interrupt request held pending reset processing interval timer no yes yes no yes no yes no yes no start
416 chapter 19 interrupt and test functions users manual u10105ej4v1um00 figure 19-12. non-maskable interrupt request acknowledge operation (a) if a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution main routine nmi request 1 instruction execution nmi request nmi request reserve reserved nmi request processing (b) if two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution main routine nmi request 1 instruction execution nmi request reserved although two or more nmi requests have been generated, only one request has been acknowledged. nmi request reserved
417 chapter 19 interrupt and test functions users manual u10105ej4v1um00 19.4.2 maskable interrupt acknowledge operation a maskable interrupt becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mk flag is cleared to 0. a vectored interrupt is acknowledged in an interrupt enable state (with ie flag set to 1). however, a low-priority interrupt is not acknowledged during high-priority interrupt service (with isp flag reset to 0). wait times maskable interrupt request generation to interrupt servicing are as follows. table 19-3. times from maskable interrupt request generation to interrupt service minimum time maximum time note when pr = 0 7 clock cycles 32 clock cycles when pr = 1 8 clock cycles 33 clock cycles note if an interrupt request is generated just before a divide instruction, the wait time is maximized. remark 1 clock cycle = 1/cpu clock frequency (f cpu ) if two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority with the priority specify flag is acknowledged first. two or more requests specified for the same priority, the default priorities apply. any reserved interrupts are acknowledged when they become acknowledgeable. figure 19-13 shows interrupt acknowledge algorithms. if a maskable interrupt request is acknowledged, the acknowledged interrupt is saved in the stacks, psw and pc, in that order, the ie flag is reset to 0, and the acknowledged interrupt priority specify flag contents are transferred to the isp flag. further, the vector table data determined for each interrupt request is loaded into pc and branched. return from the interrupt is possible with the reti instruction.
418 chapter 19 interrupt and test functions users manual u10105ej4v1um00 figure 19-13. interrupt acknowledge processing algorithm start if=1? mk=0? pr=0? any simultaneously generated pr=0 interrupts? any simultaneously generated high-priority interrupts? ie=1? isp=1? vectored interrupt servicing interrupt request reserve interrupt request reserve interrupt request reserve interrupt request reserve interrupt request reserve interrupt request reserve interrupt request reserve vectored interrupt servicing any high- priority interrupt among simultaneously generated pr=0 interrupts? ie=1? yes (high priority) yes no yes no no no yes (interrupt request generation) no yes no (low priority) yes yes no yes yes no no
419 chapter 19 interrupt and test functions users manual u10105ej4v1um00 figure 19-14. interrupt acknowledge timing (minimum time) remark 1 clock cycle = 1/cpu clock frequency (f cpu ) figure 19-15. interrupt acknowledge timing (maximum time) remark 1 clock cycle = 1/cpu clock frequency (f cpu ) instruction divide instruction psw and pc save, jump to interrupt servicing 6 clocks interrupt servicing program 8 clocks 7 clocks cpu processing if ( pr=1) if ( pr=0) instruction divide instruction psw and pc save, jump to interrupt servicing 6 clocks interrupt servicing program 33 clocks 32 clocks cpu processing if ( pr=1) if ( pr=0) 25 clocks
420 chapter 19 interrupt and test functions users manual u10105ej4v1um00 interrupt being acknowledged non-maskable interrupt request multiple interrupt request maskable interrupt servicing 19.4.3 software interrupt acknowledge operation a software interrupt is acknowledged by brk instruction execution. software interrupt cannot be disabled. if a software interrupt is acknowledged, it is saved in the stacks, psw and pc, in that order, the ie flag is reset to 0 and the contents of the vector tables (003eh and 003fh) are loaded into pc and branched. return from the software interrupt is possible with the retb instruction. caution do not use the reti instruction for returning from the software interrupt. 19.4.4 multiple interrupt servicing multiple interrupts, in which another interrupt is acknowledged during execution of an interrupt, can be controlled by priorities. two types of priority control are available; control in the order of default priority and programmable priority control by setting the priority specify flag registers (pr0l, pr0h and pr1l). in the former, if two or more interrupts are generated simultaneously, interrupt servicing is carried out in accordance with the priority (default priority) preassigned to each interrupt request (see table 19-1 ). in the latter, interrupt requests are divided into a high-priority group and a low-priority group by setting the bits corresponding to pr0l, pr0h, and pr1l. the following are the interrupt requests enabled for multiple interrupts. table 19-4. interrupt request enabled for multiple interrupt during interrupt servicing maskable interrupt request pr=0 pr=1 ie=1 ie=0 ie=1 ie=0 non-maskable interrupt servicing d d d d d isp=0 e e d d d isp=1 e e d e d software interrupt servicing e e d e d remarks 1. e : multiple interrupt enable 2. d : multiple interrupt disable 3. isp and ie are the flags contained in psw isp=0 : an interrupt with higher priority is being serviced isp=1 : an interrupt is not accepted or an interrupt with lower priority is being serviced ie=0 : interrupt acknowledge is disabled ie=1 : interrupt acknowledge is enabled 4. pr is a flag contained in pr0l, pr0h, pr1l pr=0 : higher priority level pr=1 : lower priority level
421 chapter 19 interrupt and test functions users manual u10105ej4v1um00 figure 19-16. multiple interrupt example example 1 main processing ei intxx (pr=1) intyy (pr=0) ie=0 ei reti intxx servicing intzz (pr=0) ie=0 ei reti intyy servicing ie=0 reti intzz servicing example 2 main processing intxx servicing intyy servicing intxx (pr=0) ie=1 1 instruction execution ie=0 intyy (pr=1) ei ie=0 ei reti reti example 3 main processing intxx servicing intyy servicing intxx (pr=0) 1 instruction execution ie=0 intyy (pr=0) ie=0 reti reti ei
422 chapter 19 interrupt and test functions users manual u10105ej4v1um00 19.4.5 interrupt reserve interrupt acknowledge is temporarily reserved between any of the following instructions and the next instruction to be executed. ? mov psw, #byte ? mov a, psw ? mov psw, a ? mov1 psw.bit, cy ? mov1 cy, psw.bit ? and1 cy, psw.bit ? or1 cy, psw.bit ? xor1 cy, psw.bit ? set1 psw.bit ? clr1 psw.bit ? retb ? reti ? push psw ? pop psw ? bt psw.bit, $addr16 ? bf psw.bit, $addr16 ? btclr psw.bit, $addr16 ?ei ?di ? manipulate instructions for if0l, if0h, if1l, mk0l, mk0h, mk1l, pr0l, pr0h, pr1l, intm0, intm1 registers caution because the ie flag is cleared to 0 by the software interrupt (by executing the brk instruction), interrupts are not acknowledged even when a maskable interrupt request is issued during the execution of the brk instruction. however, non-maskable interrupt requests are acknowledged. figure 19-17. interrupt request hold remarks 1. instruction n: instruction that holds interrupts requests 2. instruction m: instructions other than interrupt request pending instruction 3. the pr values do not affect the operation of if. cpu processing if instruction n instruction m save psw and pc, jump to interrupt service interrupt service program
423 chapter 19 interrupt and test functions users manual u10105ej4v1um00 19.5 test functions vector processing is not performed, but the test input flag is set to 1. in this function, the standby release signal is generated. there are two test input factors as shown in table 19-5. the basic configuration is shown in figure 19-18. table 19-5. test input factors test input factors internal/ name trigger external intwt watch timer overflow internal intpt11 falling edge detection at port 11 external figure 19-18. basic configuration of test function if: test input flag mk: test mask flag 19.5.1 registers controlling the test function the test function is controlled by the following three registers. ? interrupt request flag register 1l (if1l) ? interrupt mask flag register 1l (mk1l) ? key return mode register (krm) the names of the test input flags and test mask flags corresponding to the test input signals are listed in table 19-6. table 19-6. flags corresponding to test input signals test input signal name test input flag test mask flag intwt wtif wtmk intpt11 krif krmk internal bus mk if test input signal standby release signal
424 chapter 19 interrupt and test functions users manual u10105ej4v1um00 (1) interrupt request flag register 1l (if1l) it indicates whether a watch timer overflow is detected or not. it is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. it is set to 00h by the reset signal input. figure 19-19. format of interrupt request flag register 1l caution be sure to set bits 3 through 6 to 0. (2) interrupt mask flag register 1l (mk1l) it is used to set the standby mode enable/disable at the time the standby mode is released by the watch timer. it is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. it is set to ffh by the reset signal input. figure 19-20. format of interrupt mask flag register 1l caution be sure to set bits 3 through 6 to 1. 7 wtif symbol if1l 6 0 5 0 4 0 3 0 2 adif 1 tmif2 0 tmif1 address ffe2h 00h when reset r/w r/w 0 1 watch timer overflow detection flag not detected detected wtif 7 wtmk symbol mk1l 6 1 5 1 4 0 3 0 210 address ffe6h ffh when reset r/w r/w 0 1 standby mode control by watch timer enables releasing the standby mode. disables releasing the standby mode. wtmk admk tmmk2 tmmk1
425 chapter 19 interrupt and test functions users manual u10105ej4v1um00 (3) key return mode register (krm) this register is used to set enable/disable of standby function clear by key return signal (port 11 falling edge detection), and selects port 11 falling edge input. krm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets krm to 02h. figure 19-21. key return mode register format caution when port 11 falling edge detection is used, be sure to clear krif to 0 (not cleared to 0 automatically). 7 0 symbol krm 6 0 5 0 4 0 3 krm3 2 krm2 1 krmk 0 krif address ffb8h 02h when reset r/w r/w 0 1 key return signal not detected detected (port 11 falling edge detection) krif 0 1 standby mode control by key return signal standby mode release enabled standby mode release disabled krmk krm3 selection of port 11 falling edge input 0 0 p117 krm2 0 1 1 1 0 1 p114-p117 p112-p117 p110-p117
426 chapter 19 interrupt and test functions users manual u10105ej4v1um00 19.5.2 test input signal acknowledge operation (1) internal test signal if the watch timer overflows, the wtif flag is set. the watch function is available by checking the wtif flag at a shorter cycle than the watch timer overflow cycle. (2) external test signal when a falling edge is input to the port 4 (p110 to p117) pins, krif is set. if port 11 is used as key matrix return signal input, whether or not a key input has been applied can be checked from the krif status.
427 users manual u10105ej4v1um00 chapter 20 standby function 20.1 standby function and configuration 20.1.1 standby function the standby function is designed to decrease power consumption of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. the halt mode is intended to stop the cpu operation clock. system clock oscillator continues oscillation. in this mode, current consumption cannot be decreased as in the stop mode. the halt mode is valid to restart immediately upon interrupt request and to carry out intermittent operations such as in watch applications. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the main system clock oscillator stops and the whole system stops. cpu current consumption can be considerably decreased. data memory low-voltage hold (down to v dd = 1.8 v) is possible. thus, the stop mode is effective to hold data memory contents with ultra-low current consumption. because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. however, because a wait time is necessary to secure an oscillation stabilization time after the stop mode is cleared, select the halt mode if it is necessary to start processing immediately upon interrupt request. in any mode, all the contents of the register, flag and data memory just before standby mode setting are held. the input/output port output latch and output buffer statuses are also held. cautions 1. the stop mode can be used only when the system operates with the main system clock (subsystem clock oscillation cannot be stopped). the halt mode can be used with either the main system clock or the subsystem clock. 2. when proceeding to the stop mode, be sure to stop the peripheral hardware operation and execute the stop instruction. 3. the following sequence is recommended for power consumption reduction of the a/d converter when the standby function is used: first clear bit 7 (cs) of adm to 0 to stop the a/d conversion operation, and then execute the halt or stop instruction. * *
428 chapter 20 standby function users manual u10105ej4v1um00 20.1.2 standby function control register a wait time after the stop mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (osts). osts is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. however, it takes 2 17 /f x , not 2 18 /f x , until the stop mode is cleared by reset input. figure 20-1. oscillation stabilization time select register format caution the wait time after stop mode clear does not include the time (see "a" in the illustration below) from stop mode clear to clock oscillation start, regardless of clearance by reset input or by interrupt generation. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs : oscillation mode select register bit 0 4. values in parentheses apply to operating at f x = 5.0 mhz address fffah 04h after reset r/w r/w 0 0 0 0 1 selection of oscillation stabilization time when stop mode is released 2 12 /f xx 2 14 /f xx 2 15 /f xx 2 16 /f xx 2 17 /f xx osts2 7 0 symbol osts 6 0 5 0 4 0 3 0 2 osts2 1 osts1 0 osts0 0 0 1 1 0 other than above osts1 mcs = 1 mcs = 0 2 12 /f x (819 s) 2 14 /f x (3.28 ms) 2 15 /f x (6.55 ms) 2 16 /f x (13.1 ms) 2 17 /f x (26.2 ms) 2 13 /f x (1.64 ms) 2 15 /f x (6.55 ms) 2 16 /f x (13.1 ms) 2 17 /f x (26.2 ms) 2 18 /f x (52.4 ms) m 0 1 0 1 0 osts0 setting prohibited stop mode clear x1 pin voltage waveform v ss a
429 chapter 20 standby function users manual u10105ej4v1um00 20.2 standby function operations 20.2.1 halt mode (1) halt mode set and operating status the halt mode is set by executing the halt instruction. it can be set with the main system clock or the subsystem clock. the operating status in the halt mode is described below. table 20-1. halt mode operating status halt mode setting halt execution during halt execution during main system clock operation subsystem clock operation w/ subsystem w/o. subsystem main system main system item clock ( note1 ) clock ( note2 ) clock oscillates clock stops clock generator both main system and subsystem clocks can be oscillated. clock supply to the cpu stops. cpu operation stop. port (output latch) status before halt mode setting is held. 16-bit timer/event counter operable. operable when watch timer output with f xt selected as count clock (f xt is selected as count clock for watch timer). 8-bit timer/event counter 1 and 2 operable. operablewhen ti1 or ti2 is selected as count clock. watch timer operable if f xx /2 7 operable. operable if f xt is selected as is selected as count clock. count clock. watchdog timer operable. operable. a/d converter operable. operation stops. serial interface operable operable at external sck. lcd controller/driver operable if f xx /2 7 operable. operable if f xt is selected as is selected as count clock. count clock. external intp0 operable when a clock (f xx /2 5 , f xx /2 6 , f xx /2 7 ) for the operation stops. interrupt peripheral hardware is selected as sampling clock. intp1 to intp5 operable. notes 1. including case when external clock is supplied. 2. including case when external clock is not supplied. *
430 chapter 20 standby function users manual u10105ej4v1um00 (2) halt mode clear the halt mode can be cleared with the following four types of sources. (a) clear upon unmasked interrupt request an unmasked interrupt request is used to clear the halt mode. if interrupt acknowledge is enabled, vectored interrupt service is carried out. if disabled, the next address instruction is executed. figure 20-2. halt mode clear upon interrupt generation halt instruction wait standby release signal operating mode clock halt mode wait oscillation operating mode remarks 1. the broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged. 2. wait time will be as follows: ? when vectored interrupt service is carried out: 8 to 9 clocks ? when vectored interrupt service is not carried out: 2 to 3 clocks (b) clear upon non-maskable interrupt request the halt mode is cleared and vectored interrupt service is carried out whether interrupt acknowledge is enabled or disabled. (c) clear upon unmasked test input the halt mode is cleared by unmasked test input and the next address instruction of the halt instruction is executed.
431 chapter 20 standby function users manual u10105ej4v1um00 (d) clear upon reset input as is the case with normal reset operation, a program is executed after branch to the reset vector address. figure 20-3. halt mode release by reset input remarks 1. f x : main system clock oscillation frequency 2. time value in parentheses is when f x = 5.0 mhz. table 20-2. operation after halt mode release release source mk pr ie isp operation maskable interrupt 0 0 0 next address instruction execution request 0 0 1 interrupt service execution 0 1 0 1 next address instruction execution 01 0 0 1 1 1 interrupt service execution 1 halt mode hold non-maskable interrupt C C interrupt service execution request test input 0 C next address instruction execution 1C halt mode hold reset input C C reset processing x: don't care halt instruction reset signal operating mode clock reset period halt mode oscillation oscillation stop oscillation stabilization wait status operating mode oscillation wait (2 17 /f x : 26.2 ms)
432 chapter 20 standby function users manual u10105ej4v1um00 20.2.2 stop mode (1) stop mode set and operating status the stop mode is set by executing the stop instruction. it can be set only with the main system clock. cautions 1. when the stop mode is set, the x2 pin is internally connected to v dd via a pull-up resistor to minimize the leakage current at the crystal oscillator. thus, do not use the stop mode in a system where an external clock is used for the main system clock. 2. because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction. after the wait set using the oscillation stabilization time select register (osts), the operating mode is set. the operating status in the stop mode is described below. table 20-3. stop mode operating status stop mode setting with subsystem clock without subsystem clock item clock generator only main system clock stops oscillation. cpu operation stop. port (output latch) status before stop mode setting is held. 16-bit timer/event counter operable when watch timer output with f xt selected operation stops. is selected as count clock (f xt is selected as count clock for watch timer). 8-bit timer/event counter 1 and 2 operable when ti1 and ti2 are selected for the count clock. watch timer operable when f xt is selected for the count clock. operation stops. watchdog timer operation stops. a/d converter operation stops. serial other than uart operable when externally supplied clock is specified as the serial clock. interface uart operation stops. lcd controller/driver operable when f xt is selected for the count clock. operation stops. external intp0 operation is impossible. interrupt intp1 to intp5 operable. * *
433 chapter 20 standby function users manual u10105ej4v1um00 (2) stop mode release the stop mode can be cleared with the following three types of sources. (a) release by unmasked interrupt request an unmasked interrupt request is used to release the stop mode. if interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. if interrupt acknowledge is disabled, the next address instruction is executed. figure 20-4. stop mode release by interrupt generation stop instruction wait (time set by osts) oscillation stabilization wait status operating mode oscillation operationg mode stop mode oscillation stop oscillation standby release signal clock remark the broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged. (b) release by unmasked test input the stop mode is cleared by unmasked test input. after the lapse of oscillation stabilization time, the instruction at the next address of the stop instruction is executed.
434 chapter 20 standby function users manual u10105ej4v1um00 (c) release by reset input the stop mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried out. figure 20-5. release by stop mode reset input remarks 1. f x : main system clock oscillation frequency 2. time value in parentheses is when f x = 5.0 mhz. table 20-4. operation after stop mode release release source mk pr ie isp operation maskable interrupt request 0 0 0 next address instruction execution 001 interrupt service execution 0 1 0 1 next address instruction execution 01 0 0 1 1 1 interrupt service execution 1 stop mode hold test input 0 C next address instruction execution 1C stop mode hold reset input C C reset processing : don't care reset signal operating mode clock reset period stop mode oscillation stop oscillation stabilization wait status operating mode oscillation wait (2 17 /f x : 26.2 ms) stop instruction oscillation
435 users manual u10105ej4v1um00 chapter 21 reset function 21.1 reset function the following two operations are available to generate the reset signal. (1) external reset input with reset pin (2) internal reset by watchdog timer overrun time detection external reset and internal reset have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h by reset input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status as shown in table 21-1. each pin has high impedance during reset input or during oscillation stabilization time just after reset clear. when a high level is input to the reset input, the reset is cleared and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ). the reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ) (see figure 21-2 to 21- 4 ). cautions 1. for an external reset, input a low level for 10 m s or more to the reset pin. 2. during reset input, main system clock oscillation remains stopped but subsystem clock oscillation continues. 3. when the stop mode is cleared by reset, the stop mode contents are held during reset input. however, the port pin becomes high-impedance. figure 21-1. block diagram of reset function reset count clock reset control circuit watchdog timer stop over- flow reset signal interrupt function
436 chapter 21 reset function users manual u10105ej4v1um00 figure 21-2. timing of reset input by reset input figure 21-3. timing of reset due to watchdog timer overflow figure 21-4. timing of reset input in stop mode by reset input x1 normal operation watchdog timer overflow internal reset signal port pin reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) high impedance reset internal reset signal port pin delay delay high impedance x1 normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) stop status (oscillation stop) stop instruction execution reset internal reset signal port pin delay delay high impedance x1 normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing)
437 chapter 21 reset function users manual u10105ej4v1um00 table 21-1. hardware status after reset (1/2) hardware status after reset program counter (pc) note1 the contents of reset vector tables (0000h and 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h ram data memory undefined note2 general register undefined note2 port (output latch) ports 0 to 3, port 7 to 11 (p0-p3, p7-p11) 00h port mode register (pm0 to pm3, pm5 to pm7, pm12, pm13) ffh pull-up resistor option register (puoh, puol) 00h processor clock control register (pcc) 04h oscillation mode selection register (osms) 00h memory size switching register (ims) note3 oscillation stabilization time select register (osts) 04h 16-bit timer/event counter timer register (tm0) 00h capture/compare register (cr00, cr01) undefined clock selection register (tcl0) 00h mode control register (tmc0) 00h capture/compare control register 0 (crc0) 04h output control register (toc0) 00h 8-bit timer/event counter 1, 2 timer register (tm1, tm2) 00h compare registers (cr10, cr20) undefined clock select register (tcl1) 00h mode control registers (tmc1) 00h output control register (toc1) 00h notes 1. during reset input or oscillation stabilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remains unchanged after reset. 2. the post-reset status is held in the standby mode. 3. the values after reset depend on the product. m pd78062, 78062y : 44h, m pd78063, 78063y : c6h, m pd78064, 78064y : c8h, m pd78p064, 78p064y : c8h
438 chapter 21 reset function users manual u10105ej4v1um00 table 21-1. hardware status after reset (2/2) hardware status after reset watch timer mode control register (tmc2) 00h clock select register (tcl2) 00h watchdog timer mode register (wdtm) 00h serial interface clock select register (tcl3) 88h shift registers (sio0) undefined mode registers (csim0, csim2) 00h serial bus interface control register (sbic) 00h slave address register (sva) undefined asynchronous serial interface mode register (asim) 00h asynchronous serial interface status register (asis) 00h baud rate generator control register (brgc) 00h transmit shift register (txs) ffh receive buffer register (rxb) interrupt timing specify register (sint) 00h a/d converter mode register (adm) 01h conversion result register (adcr) undefined input select register (adis) 00h lcd controller/driver display mode register (lcdm) 00h display control register (lcdc) 00h interrupt request flag register (if0l, if0h, if1l) 00h mask flag register (mk0l, mk0h, mk1l) ffh priority specify flag register (pr0l, pr0h, pr1l) ffh external interrupt mode register (intm0, intm1) 00h key return mode register (krm) 02h sampling clock select register (scs) 00h *
439 users manual u10105ej4v1um00 chapter 22 m pd78p064, 78p064y the m pd78p064, 78p064y replace the internal mask rom of the m pd78064, 78064y with one-time prom or eprom. table 22-1 lists the differences among the m pd78p064, 78p064y and the mask rom versions. table 22-1. differences among m pd78p064, 78p064y and mask rom versions item m pd78p064, 78p064y mask rom versions ic pin none available v pp pin available none on-chip mask option none available split resistors for lcd driving power supply
440 chapter 22 m pd78p064, 78p064y users manual u10105ej4v1um00 22.1 memory size switching register the m pd78p064, 78p064y allows users to define its internal rom and high-speed ram sizes using the memory size switching register (ims), so that the same memory mapping as that of a mask rom version with a different- size internal rom and high-speed ram is possible. ims is set with an 8-bit memory manipulation instruction. reset input sets ims to c8h. figure 22-1. memory size switching register format 7 ram2 symbol ims 6 ram1 5 ram0 4 0 3 rom3 2 rom2 1 rom1 0 rom0 address fff0h c8h after reset r/w r/w 1 internal rom capacity selection 32 kbytes rom3 0 rom2 0 rom1 0 rom0 setting prohibited other than above internal high-speed ram capacity selection ram2 ram1 ram0 512 bytes 010 setting prohibited other than above 0 0 16 kbytes 24 kbytes 1 1 0 1 0 0 1024 bytes 110 the ims settings to give the same memory map as mask rom versions are shown in table 22-2. table 22-2. examples of memory size switching register settings relevant mask rom version ims setting m pd78062, 78062y 44h m pd78063, 78063y c6h m pd78064, 78064y c8h
441 chapter 22 m pd78p064, 78p064y users manual u10105ej4v1um00 22.2 prom programming the m pd78p064 and 78p064y each incorporate a 32-kbyte prom as program memory. to write a program into the m pd78p054 or 78p058 prom, make the device enter the prom programming mode by setting the levels of the v pp and reset pins as specified. for the connection of unused pins, see paragraph (2) prom programming mode in section 1.4 . caution write the program in the range of addresses 0000h to 7fffh (specify the last address as 7fffh.) the program cannot be correctly written by a prom programmer which does not have a write address specification function. 22.2.1 operating modes when +5 v or +12.5 v is applied to the v pp pin and a low-level signal is applied to the reset pin, the m pd78p064 and m pd78p064y are set to the prom programming mode. this is one of the operating modes shown in table 22-3 below according to the setting of the ce, oe, and pgm pins. the prom contents can be read by setting the read mode. table 22-3. prom programming operating modes pin operating mode page data latch l +12.5 v +6.5 v h l h data input page write h h l high impedance byte write l h l data input program verify l l h data output program inhibit h h high impedance ll read +5 v +5v l l h data output output disabled l h high impedance standby h high impedance : l or h (1) read mode read mode is set by setting ce to l and oe to l. (2) output disable mode if oe is set to h, data output becomes high impedance and the output disable mode is set. therefore, if multiple m pd78p064s or 78p064ys are connected to the data bus, data can be read from any one device by controlling the oe pin. reset v pp v dd ce oe pgm d0-d7
442 chapter 22 m pd78p064, 78p064y users manual u10105ej4v1um00 (3) standby mode setting ce to h sets the standby mode. in this mode, data output becomes high impedance irrespective of the status of oe. (4) page data latch mode setting ce to h, pgm to h, and oe to l at the start of the page write mode sets the page data latch mode. in this mode, 1-page 4-byte data is latched in the internal address/data latch circuit. (5) page write mode after a 1-page 4-byte address and data are latched by the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active-low) to the pgm pin while ce=h and oe=h. after this, program verification can be performed by setting ce to l and oe to l. if programming is not performed by one program pulse, repeated write and verify operations are executed x times (x 10). (6) byte write mode a byte write is executed by applying a 0.1-ms program pulse (active-low) to the pgm pin while ce=l and oe=h. after this, program verification can be performed by setting oe to l. if programming is not performed by one program pulse, repeated write and verify operations are executed x times (x 10). (7) program verify mode setting ce to l, pgm to h, and oe to l sets the program verify mode. after writing is performed, this mode should be used to check whether the data was written correctly. (8) program inhibit mode the program inhibit mode is used when the oe pins, v pp pins and pins d0 to d7 of multiple m pd78p064s or 78p064ys are connected in parallel and any one of these devices must be written to. the page write mode or byte write mode described above is used to perform a write. at this time, the write is not performed on the device which has the pgm pin driven high.
443 chapter 22 m pd78p064, 78p064y users manual u10105ej4v1um00 22.2.2 prom write procedure figure 22-2. page program mode flowchart start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 latch address = address + 1 latch address = address + 1 latch address = address + 1 latch x = x + 1 0.1-ms program pulse verify 4 bytes pass address = n? no pass v dd = 4.5 to 5.5 v, v pp = v dd all bytes verified? end of write address = address + 1 no yes x = 10? fail fail yes all pass defective product remark: g = start address n = last address of program
444 chapter 22 m pd78p064, 78p064y users manual u10105ej4v1um00 figure 22-3. page program mode timing page data latch page program program verify data input data output a2-a16 a0, a1 d0-d7 v pp v dd v pp v dd +1.5 v dd v dd v ih ce pgm oe v il v ih v il v ih v il
445 chapter 22 m pd78p064, 78p064y users manual u10105ej4v1um00 figure 22-4. byte program mode flowchart start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 x = x + 1 0.1-ms program pulse verify address = n? v dd = 4.5 to 5.5 v, v pp = v dd all bytes verified? end of write fail fail pass yes all pass no pass defective product no yes x = 10? address = address + 1 remark: g = start address n = last address of program
446 chapter 22 m pd78p064, 78p064y users manual u10105ej4v1um00 figure 22-5. byte program mode timing cautions 1. be sure to apply v dd before applying v pp , and remove it after removing v pp . 2. v pp must not exceed +13.5 v including overshoot voltage. 3. disconnecting/inserting the device from/to the on-board socket while +12.5 v is being applied to the v pp pin may have an adverse affect on device reliability. a0-a16 d0-d7 program program verify data input data output v pp v dd v dd +1.5 v dd v ih v il v ih v il v ih v il v pp v dd ce pgm oe
447 chapter 22 m pd78p064, 78p064y users manual u10105ej4v1um00 22.2.3 prom reading procedure prom contents can be read onto the external data bus (d0 to d7) using the following procedure. (1) fix the reset pin low, and supply +5 v to the v pp pin. unused pins are handled as shown in paragraph, (2) prom programming mode in section 1.4 . (2) supply +5 v to the v dd and v pp pins. (3) input the address of data to be read to pins a0 through a16. (4) read mode is entered. (5) data is output to pins d0 through d7. the timing for steps (2) through (5) above is shown in figure 22-6. figure 22-6. prom read timing address input a0-a16 ce (input) oe (input) d0-d7 hi-z data output hi-z
448 chapter 22 m pd78p064, 78p064y users manual u10105ej4v1um00 22.3 erasure procedure ( m pd78p064kl-t and 78p064ykl-t only) with the m pd78p064kl-t or 78p064ykl-t, it is possible to erase ( or set all contents to ffh) the data contents written in the program memory, and rewrite the memory. the data can be erased by exposing the window to light with a wavelength of approximately 400 nm or shorter. typically, data is erased by 254-nm ultraviolet light rays. the minimum lighting level to completely erase the written data is shown below. ? uv intensity exposure time: 15 w . s/cm 2 or more ? exposure time: 15 to 20 minutes (using a 12 mw/cm 2 ultraviolet lamp. a longer exposure time may be required in case of deterioration of the ultraviolet lamp or dirt on the package window). when erasing written data, remove any filter on the window and place the device within 2.5 cm of the lamp tube. 22.4 opaque film masking the window ( m pd78p064kl-t and 78p064ykl-t only) to prevent unintentional erasure of the eprom contents by light and to prevent internal circuits from mulfunction due to light coming in through the erasure window, mask the window with opaque film after writing the eprom. 22.5 screening of one-time prom versions one-time prom versions ( m pd78p064gc-7ea, m pd78p064ygc-7ea, m pd78p064gf-3ba, and m pd78p064ygf-3ba) cannot be fully tested by nec before shipment due to the structure of one-time prom. therefore, after users have written data into the prom, screening should be implemented by user: that is, store devices at high temperature for one day as specified below, and verify their contents after the devices have returned to room temperature. storage temperature storage time 125 c 24 hours for users who do not wish to implement screening by themselves, nec provides such users with a charged service in which nec performs a series of processes from writing one-time proms and screening them to verifying their contents for users by request. the prom version devices which provide this service are called qtop tm microcontrollers. for details, please consult an nec sales representative. *
449 users manual u10105ej4v1um00 chapter 23 instruction set this chapter describes each instruction set of the m pd78064 and 78064y subseries as list table. for details of its operation and operation code, refer to the separate document 78k/0 series users manualinstruction (u12326e) .
450 chapter 23 instruction set users manual u10105ej4v1um00 23.1 legends used in operation list 23.1.1 operand identifiers and description methods operands are described in operand column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description methods, select one of them. alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be described as they are. each symbol has the following meaning. ? # : immediate data specification ? ! : absolute address specification ? $ : relative address specification ? [ ] : indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $, and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 23-1. operand identifiers and description methods identifier description method r x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7), rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special-function register symbol note sfrp special-function register symbol (16-bit manipulatable register even addresses only) note saddr fe20h-ff1fh immediate data or labels saddrp fe20h-ff1fh immediate data or labels (even address only) addr16 0000h-ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) addr11 0800h-0fffh immediate data or labels addr5 0040h-007fh immediate data or labels (even address only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh cannot be accessed with these operands. remark for special-function register symbols, refer to table 5-4 special-function register list .
451 chapter 23 instruction set users manual u10105ej4v1um00 23.1.2 description of operation column a : a register; 8-bit accumulator x : x register b : b register c : c register d : d register e : e register h : h register l : l register ax : ax register pair; 16-bit accumulator bc : bc register pair de : de register pair hl : hl register pair pc : program counter sp : stack pointer psw : program status word cy : carry flag ac : auxiliary carry flag z : zero flag rbs : register bank select flag ie : interrupt request enable flag nmis : non-maskable interrupt servicing flag ( ) : memory contents indicated by address or register contents in parentheses h , l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) : inverted data addr16 : 16-bit immediate data or label jdisp8 : signed 8-bit data (displacement value) 23.1.3 description of flag operation column (blank) : nt affected 0 : cleared to 0 1 : set to 1 : set/cleared according to the result r : previously saved value is restored
452 chapter 23 instruction set users manual u10105ej4v1um00 23.2 operation list clock flag note 1 note 2 zaccy r, #byte 2 4 C r ? byte saddr, #byte 3 6 7 (saddr) ? byte sfr, #byte 3 C 7 sfr ? byte a, r note 3 12 Ca ? r r, a note 3 12 Cr ? a a, saddr 2 4 5 a ? (saddr) saddr, a 2 4 5 (saddr) ? a a, sfr 2 C 5 a ? sfr sfr, a 2 C 5 sfr ? a a, !addr16 3 8 9 a ? (addr16) !addr16, a 3 8 9 (addr16) ? a psw, #byte 3 C 7 psw ? byte a, psw 2 C 5 a ? psw psw, a 2 C 5 psw ? a a, [de] 1 4 5 a ? (de) [de], a 1 4 5 (de) ? a a, [hl] 1 4 5 a ? (hl) [hl], a 1 4 5 (hl) ? a a, [hl + byte] 2 8 9 a ? (hl + byte) [hl + byte], a 2 8 9 (hl + byte) ? a a, [hl + b] 1 6 7 a ? (hl + b) [hl + b], a 1 6 7 (hl + b) ? a a, [hl + c] 1 6 7 a ? (hl + c) [hl + c], a 1 6 7 (hl + c) ? a a, r note 3 12 Ca ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 C 6 a ? (sfr) a, !addr16 3 8 10 a ? (addr16) xch a, [de] 1 4 6 a ? (de) a, [hl] 1 4 6 a ? (hl) a, [hl + byte] 2 8 10 a ? (hl + byte) a, [hl + b] 2 8 10 a ? (hl + b) a, [hl + c] 2 8 10 a ? (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except "r = a" remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. mnemonic operands byte operation instruction group mov 8-bit data transfer
453 chapter 23 instruction set users manual u10105ej4v1um00 clock flag note 1 note 2 zaccy rp, #word 3 6 C rp ? word saddrp, #word 4 8 10 (saddrp) ? word sfrp, #word 4 C 10 sfrp ? word ax, saddrp 2 6 8 ax ? (saddrp) saddrp, ax 2 6 8 (saddrp) ? ax movw ax, sfrp 2 C 8 ax ? sfrp sfrp, ax 2 C 8 sfrp ? ax ax, rp note 3 1 4 C ax ? rp rp, ax note 3 1 4 C rp ? ax ax, !addr16 3 10 12 ax ? (addr16) !addr16, ax 3 10 12 (addr16) ? ax xchw ax, rp note 3 1 4 C ax ? rp a, #byte 2 4 C a, cy ? a + byte saddr, #byte 3 6 8 (saddr), cy ? (saddr) + byte a, r note 4 2 4 C a, cy ? a + r r, a 2 4 C r, cy ? r + a a, saddr 2 4 5 a, cy ? a + (saddr) a, !addr16 3 8 9 a, cy ? a + (addr16) a, [hl] 1 4 5 a, cy ? a + (hl) a, [hl + byte] 2 8 9 a, cy ? a + (hl + byte) a, [hl + b] 2 8 9 a, cy ? a + (hl + b) a, [hl + c] 2 8 9 a, cy ? a + (hl + c) a, #byte 2 4 C a, cy ? a + byte + cy saddr, #byte 3 6 8 (saddr), cy ? (saddr) + byte + cy a, r note 4 2 4 C a, cy ? a + r + cy r, a 2 4 C r, cy ? r + a + cy a, saddr 2 4 5 a, cy ? a + (saddr) + cy a, !addr16 3 8 9 a, cy ? a + (addr16) + cy a, [hl] 1 4 5 a, cy ? a + (hl) + cy a, [hl + byte] 2 8 9 a, cy ? a + (hl + byte) + cy a, [hl + b] 2 8 9 a, cy ? a + (hl + b) + cy a, [hl + c] 2 8 9 a, cy ? a + (hl + c) + cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except "r = a" remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. mnemonic operands byte operation instruction group 16-bit data transfer add addc 8-bit operation
454 chapter 23 instruction set users manual u10105ej4v1um00 clock flag note 1 note 2 zaccy a, #byte 2 4 C a, cy ? a C byte saddr, #byte 3 6 8 (saddr), cy ? (saddr) C byte a, r note 3 2 4 C a, cy ? a C r r, a 2 4 C r, cy ? r C a a, saddr 2 4 5 a, cy ? a C (saddr) a, !addr16 3 8 9 a, cy ? a C (addr16) a, [hl] 1 4 5 a, cy ? a C (hl) a, [hl + byte] 2 8 9 a, cy ? a C (hl + byte) a, [hl + b] 2 8 9 a, cy ? a C (hl + b) a, [hl + c] 2 8 9 a, cy ? a C (hl + c) a, #byte 2 4 C a, cy ? a C byte C cy saddr, #byte 3 6 8 (saddr), cy ? (saddr) C byte C cy a, r note 3 2 4 C a, cy ? a C r C cy r, a 2 4 C r, cy ? r C a C cy a, saddr 2 4 5 a, cy ? a C (saddr) C cy a, !addr16 3 8 9 a, cy ? a C (addr16) C cy a, [hl] 1 4 5 a, cy ? a C (hl) C cy a, [hl + byte] 2 8 9 a, cy ? a C (hl + byte) C cy a, [hl + b] 2 8 9 a, cy ? a C (hl + b) C cy a, [hl + c] 2 8 9 a, cy ? a C (hl + c) C cy a, #byte 2 4 C a ? a byte saddr, #byte 3 6 8 (saddr) ? (saddr) byte a, r note 3 24 Ca ? a r r, a 2 4 C r ? r a a, saddr 2 4 5 a ? a (saddr) a, !addr16 3 8 9 a ? a (addr16) a, [hl] 1 4 5 a ? a (hl) a, [hl + byte] 2 8 9 a ? a (hl + byte) a, [hl + b] 2 8 9 a ? a (hl + b) a, [hl + c] 2 8 9 a ? a (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except "r = a" remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. mnemonic operands byte operation instruction group sub subc and 8-bit operation
455 chapter 23 instruction set users manual u10105ej4v1um00 clock flag note 1 note 2 zaccy a, #byte 2 4 C a ? a byte saddr, #byte 3 6 8 (saddr) ? (saddr) byte a, r note 3 24 Ca ? a r r, a 2 4 C r ? r a a, saddr 2 4 5 a ? a (saddr) a, !addr16 3 8 9 a ? a (addr16) a, [hl] 1 4 5 a ? a (hl) a, [hl + byte] 2 8 9 a ? a (hl + byte) a, [hl + b] 2 8 9 a ? a (hl + b) a, [hl + c] 2 8 9 a ? a (hl + c) a, #byte 2 4 C a ? a byte saddr, #byte 3 6 8 (saddr) ? (saddr) byte a, r note 3 24 Ca ? a r r, a 2 4 C r ? r a a, saddr 2 4 5 a ? a (saddr) a, !addr16 3 8 9 a ? a (addr16) a, [hl] 1 4 5 a ? a (hl) a, [hl + byte] 2 8 9 a ? a (hl + byte) a, [hl + b] 2 8 9 a ? a (hl + b) a, [hl + c] 2 8 9 a ? a (hl + c) a, #byte 2 4 C a C byte saddr, #byte 3 6 8 (saddr) C byte a, r note 3 24 Ca C r r, a 2 4 C r C a a, saddr 2 4 5 a C (saddr) a, !addr16 3 8 9 a C (addr16) a, [hl] 1 4 5 a C (hl) a, [hl + byte] 2 8 9 a C (hl + byte) a, [hl + b] 2 8 9 a C (hl + b) a, [hl + c] 2 8 9 a C (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except "r = a" remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. mnemonic operands byte operation instruction group or xor cmp 8-bit operation
456 chapter 23 instruction set users manual u10105ej4v1um00 clock flag note 1 note 2 zaccy addw ax, #word 3 6 C ax, cy ? ax + word subw ax, #word 3 6 C ax, cy ? ax C word cmpw ax, #word 3 6 C ax C word mulu x 2 16 C ax ? a x divuw c 2 25 C ax (quotient), c (remainder) ? ax ? c r12Cr ? r + 1 saddr 2 4 6 (saddr) ? (saddr) + 1 r12Cr ? r C 1 saddr 2 4 6 (saddr) ? (saddr) C 1 incw rp 1 4 C rp ? rp + 1 decw rp 1 4 C rp ? rp C 1 ror a, 1 1 2 C (cy, a 7 ? a 0 , a m C 1 ? a m ) 1 time rol a, 1 1 2 C (cy, a 0 ? a 7 , a m + 1 ? a m ) 1 time rorc a, 1 1 2 C (cy ? a 0 , a 7 ? cy, a m C 1 ? a m ) 1 time rolc a, 1 1 2 C (cy ? a 7 , a 0 ? cy, a m + 1 ? a m ) 1 time a 3 C 0 ? (hl) 3 C 0 , (hl) 7 C 4 ? a 3 C 0 , (hl) 3 C 0 ? (hl) 7 C 4 a 3 C 0 ? (hl) 7 C 4 , (hl) 3 C 0 ? a 3 C 0 , (hl) 7 C 4 ? (hl) 3 C 0 decimal adjust accumulator after addition decimal adjust accumulator after subtract cy, saddr.bit 3 6 7 cy ? (saddr.bit) cy, sfr.bit 3 C 7 cy ? sfr.bit cy, a.bit 2 4 C cy ? a.bit cy, psw.bit 3 C 7 cy ? psw.bit cy, [hl].bit 2 6 7 cy ? (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) ? cy sfr.bit, cy 3 C 8 sfr.bit ? cy a.bit, cy 2 4 C a.bit ? cy psw.bit, cy 3 C 8 psw.bit ? cy [hl].bit, cy 2 6 8 (hl).bit ? cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. mnemonic operands byte operation instruction group inc 16-bit operation increment/ decrement dec rotate ror4 [hl] 2 10 12 rol4 [hl] 2 10 12 adjba 24 C adjbs 24 C bcd adjust mov1 bit manipu- late multiply/ divide
457 chapter 23 instruction set users manual u10105ej4v1um00 clock flag note 1 note 2 zaccy cy, saddr.bit 3 6 7 cy ? cy (saddr.bit) cy, sfr.bit 3 C 7 cy ? cy sfr.bit and1 cy, a.bit 2 4 C cy ? cy a.bit cy, psw.bit 3 C 7 cy ? cy psw.bit cy, [hl].bit 2 6 7 cy ? cy (hl).bit cy, saddr.bit 3 6 7 cy ? cy (saddr.bit) cy, sfr.bit 3 C 7 cy ? cy sfr.bit or1 cy, a.bit 2 4 C cy ? cy a.bit cy, psw.bit 3 C 7 cy ? cy psw.bit cy, [hl].bit 2 6 7 cy ? cy (hl).bit cy, saddr.bit 3 6 7 cy ? cy (saddr.bit) cy, sfr.bit 3 C 7 cy ? cy sfr.bit xor1 cy, a.bit 2 4 C cy ? cy a.bit cy, psw. bit 3 C 7 cy ? cy psw.bit cy, [hl].bit 2 6 7 cy ? cy (hl).bit saddr.bit 2 4 6 (saddr.bit) ? 1 sfr.bit 3 C 8 sfr.bit ? 1 set1 a.bit 2 4 C a.bit ? 1 psw.bit 2 C 6 psw.bit ? 1 [hl].bit 2 6 8 (hl).bit ? 1 saddr.bit 2 4 6 (saddr.bit) ? 0 sfr.bit 3 C 8 sfr.bit ? 0 clr1 a.bit 2 4 C a.bit ? 0 psw.bit 2 C 6 psw.bit ? 0 [hl].bit 2 6 8 (hl).bit ? 0 set1 cy 1 2 C cy ? 11 clr1 cy 1 2 C cy ? 00 not1 cy 1 2 C cy ? cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. mnemonic operands byte operation instruction group bit manipu- late
458 chapter 23 instruction set users manual u10105ej4v1um00 clock flag note 1 note 2 zaccy (sp C 1) ? (pc + 3) h , (sp C 2) ? (pc + 3) l , pc ? addr16, sp ? sp C 2 (sp C 1) ? (pc + 2) h , (sp C 2) ? (pc + 2) l , callf !addr11 2 5 C pc 15 C 11 ? 00001, pc 10 C 0 ? addr11, sp ? sp C 2 (sp C 1) ? (pc + 1) h , (sp C 2) ? (pc + 1) l , pc h ? (00000000, addr5 + 1), pc l ? (00000000, addr5), sp ? sp C 2 (sp C 1) ? psw, (sp C 2) ? (pc + 1) h , brk 1 6 C (sp C 3) ? (pc + 1) l , pc h ? (003fh), pc l ? (003eh), sp ? sp C 3, ie ? 0 pc h ? (sp + 1), pc l ? (sp), sp ? sp + 2 pc h ? (sp + 1), pc l ? (sp), reti 1 6 C psw ? (sp + 2), sp ? sp + 3, r r r nmis ? 0 pc h ? (sp + 1), pc l ? (sp), psw ? (sp + 2), sp ? sp + 3 psw 1 2 C (sp C 1) ? psw, sp ? sp C 1 (sp C 1) ? rp h , (sp C 2) ? rp l , sp ? sp C 2 psw 1 2 C psw ? (sp), sp ? sp + 1 r r r rp h ? (sp + 1), rp l ? (sp), sp ? sp + 2 sp, #word 4 C 10 sp ? word movw sp, ax 2 C 8 sp ? ax ax, sp 2 C 8 ax ? sp !addr16 3 6 C pc ? addr16 br $addr16 2 6 C pc ? pc + 2 + jdisp8 ax 2 8 C pc h ? a, pc l ? x bc $addr16 2 6 C pc ? pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 C pc ? pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 C pc ? pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 C pc ? pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. mnemonic operands byte operation instruction group call !addr16 3 7 C callt [addr5] 1 6 C retb 16 C rrr ret 16 C rp 1 4 C rp 1 4 C push pop uncondi- tional branch stack manipu- late conditional branch call/return
459 chapter 23 instruction set users manual u10105ej4v1um00 clock flag note 1 note 2 zaccy saddr.bit, $addr16 3 8 9 pc ? pc + 3 + jdisp8 if(saddr.bit) = 1 sfr.bit, $addr16 4 C 11 pc ? pc + 4 + jdisp8 if sfr.bit = 1 bt a.bit, $addr16 3 8 C pc ? pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 C 9 pc ? pc + 3 + jdisp8 if psw.bit = 1 [hl].bit, $addr16 3 10 11 pc ? pc + 3 + jdisp8 if (hl).bit = 1 saddr.bit, $addr16 4 10 11 pc ? pc + 4 + jdisp8 if(saddr.bit) = 0 sfr.bit, $addr16 4 C 11 pc ? pc + 4 + jdisp8 if sfr.bit = 0 bf a.bit, $addr16 3 8 C pc ? pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 C 11 pc ? pc + 4 + jdisp8 if psw. bit = 0 [hl].bit, $addr16 3 10 11 pc ? pc + 3 + jdisp8 if (hl).bit = 0 pc ? pc + 4 + jdisp8 saddr.bit, $addr16 4 10 12 if(saddr.bit) = 1 then reset(saddr.bit) pc ? pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit btclr pc ? pc + 3 + jdisp8 if a.bit = 1 then reset a.bit pc ? pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit pc ? pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit b ? b C 1, then pc ? pc + 2 + jdisp8 if b 1 0 c ? c C1, then pc ? pc + 2 + jdisp8 if c 1 0 (saddr) ? (saddr) C 1, then pc ? pc + 3 + jdisp8 if(saddr) 1 0 sel rbn 2 4 C rbs1, 0 ? n nop 1 2 C no operation ei 2 C 6 ie ? 1(enable interrupt) di 2 C 6 ie ? 0(disable interrupt) halt 2 6 C set halt mode stop 2 6 C set stop mode notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remark one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. mnemonic operands byte operation instruction group cpu control condi- tional branch sfr.bit, $addr16 4 C 12 a.bit, $addr16 3 8 C psw.bit, $addr16 4 C 12 [hl].bit, $addr16 3 10 12 b, $addr16 2 6 C dbnz c, $addr16 2 6 C saddr. $addr16 3 8 10
460 chapter 23 instruction set users manual u10105ej4v1um00 23.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz
461 chapter 23 instruction set users manual u10105ej4v1um00 second operand [hl + byte] #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + b] $addr16 1 none first operand [hl + c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp r1 dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] mov [hl + b] [hl + c] x mulu c divuw note except r = a
462 chapter 23 instruction set users manual u10105ej4v1um00 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand 1st operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand first operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 #word ax rp note sfrp saddrp !addr16 sp none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none
463 chapter 23 instruction set users manual u10105ej4v1um00 ax !addr16 !addr11 [addr5] $addr16 (4) call/instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand basic instruction br call callf callt br br bc bnc bz bnz compound bt instruction bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
464 users manual u10105ej4v1um00 [memo]
465 users manual u10105ej4v1um00 prom progammer pa-78p064gc pa-78p064gf pa-78p064kl-t programmer adapter pc-9800 series ibm pc/at and their compatibles ews (see note1 ) rs-232-c fuzzy inference development support system real-time os (rx78k/0) assembler package (ra78k/0) c compiler package (cc78k/0) screen debugger (sd78k/0) device file (df78064) rs-232-c cetronics i/f in-circuit emulator ie-78000-r ie-78064-r-em pg-1500 emulation probe ep-78064gc-r ep-78064gf-r note2 note3 note2 user system prom version pd78p064 m host machine system simulator (sm78k0) c library source file (cc78k/0-l) emulation board os (mx78k0) pg-1500 controller pd78p064y m appendix a development tools the following development tools are available for the development of systems which employ the m pd78064 and 78p064y subseries. figure a-1 shows the configuration example of the tools. figure a-1. development tool configuration notes 1 . except system simulator, screen debugger, fuzzy inference development support system, and pg- 1500 controller. 2 . ev-9200gf-100 (when ep-78064gf-r or 100-pin ceramic wqfn version is used) 3 . ev-9500gc-100 (ep-78064gc-r is used) remark though in this diagram, 3.5-inch floppy disks are shown as software delivery media. other media are also available. *
466 appendix a development tools users manual u10105ej4v1um00 a.1 language processing software ra78k/0 (assembler package) this assembler converts a program written in mnemonics into an object code executable with a microcontroller. further, this assembler is provided with functions capable of auto- matically creating symbol tables and branch instruction optimization. this data file is used together with df78064 device file (option). part number: m s ra78k0 cc78k/0 (c compiler package) this compiler converts a program written in c language into an object code executable with a microcontroller. this data file is used to- gether with ra78k/0 assembler package and df78064 device file (option). part number: m s cc78k0 df78064 (device file) (see note ) device file for the m pd78064 and 78064y subseries. this data file is used together with ra78k/0, cc78k/0, sm78k0, and sd78k/0. part number: m s df78064 cc78k/0-l (c compiler library source file) source program of a function configurating object library included in cc78k/0 c compiler. this file is necessary when customers change the object library in cc78k/0 following their specifications. part number: m s cc78k0-l note this device file can be used for any of ra78k/0, cc78k/0, sm78k0, and sd78k/0. remark of the part number differs depending on the host machine and os used. refer to the table below. m s ra78k0 m s cc78k0 m s df78064 m s cc78k0-l host machine os medium 5a13 pc-9800 series ms-dos 3.5-inch 2hd 5a10 (ver. 3.30 - 5.00a) note 5-inch 2hd 7b13 ibm pc/at or refer to section a.4. 3.5-inch 2hc 7b10 compatible machine 5-inch 2hc 3h15 hp9000 series 300 tm hp-ux tm (rel.7.05b) cartidge tape (qic-24) 3p16 hp9000 series 700 tm hp-ux (rel.9.01) digital audio tape (dat) 3k15 sparcstation tm sunos tm (rel.4.1.1) cartidge tape (qic-24) 3m15 ews-4800 series (risc) ews-ux/v (rel.4.0) note the task swap function is not available with this software though the function is provided in ms-dos version 5.0 or later. *
467 appendix a development tools users manual u10105ej4v1um00 a.2 prom programming tools hardware pg-1500 this is a prom programmer capable of programming the single-chip microcontroller incorporating prom by manipulating from the stand- alone or host machine through connection of an optional prom programmer adapter and attached board. it can also program repre- sentative proms ranging from 256k bits to 4m bits. pa-78p064gc prom programmer adapter for the m pd78p064 and 78p064y. pa-78p064gf used connected to the pg-1500. pa-78p064kl-t pa-78p064gc : 100-pin plastic qfp (14 x 14 mm) pa-78p064gf : 100-pin plastic qfp (14 20 mm) pa-78p064kl-t : 100-pin ceramic wqfn (14 20 mm) software pg-1500 controller the pg-1500 is controlled in the host machine through connection with the host machine and pg-1500 via serial and parallel interfaces. host machine os medium part number (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13pg1500 ver.3.30 to 5-inch 2hd m s5a10pg1500 ver.5.00a note ibm pc/at or refer to 3.5-inch 2hc m s7b13pg1500 compatibles section a.4. 5-inch 2hc m s7b10pg1500 note the task swap function is not available with this software though the function is provided in ms-dos version 5.0 or later.
468 appendix a development tools users manual u10105ej4v1um00 a.3 debugging tool a.3.1 hardware ie-78000-r (in-circuit emulator) this in-circuit emulator helps users in debugging hardware and software of an application system that includes a 78k/0 series device. use this in- circuit emulator in combination with an emulation probe. connect with the host machine and the prom programmer for efficient debugging. ie-78064-r-em (emulation board) this board is for the m pd78064, 78064y subseries, and supports voltages from 3 to 5.5 v. ep-78064gc-r (emulation probe) this probe is designed for 100-pin plastic qfp (14 x 14 mm) and can also be used for other devices such as the m pd78064, 78064y subseries. this probe set includes a 100-pin conversion adapter ev-9500gc-100 for easier development of user systems. tgc-100sdw (conversion adapter) this adapter connects the ep-78064gc-r to the user system board designed for 100-pin plastic qfp (14 x 14 mm). ep-78064gf-r (emulation probe) this probe is designed for 100-pin plastic qfp (14 20 mm) and can also be used for other devices such as the m pd78064, 78064y subseries. this probe set includes a 100-pin conversion socket ev-9200gf-100 for easier development of user systems. ev-9200gf-100 (conversion socket) this socket connects the ep-78064gf-r to the user system board designed for a 100-pin plastic qfp (14 20 mm). ev-9900 (device remover) this is a jig used to remove the m pd78p064kl-t and 78p064ykl-t from the ev-9200gf-100. remark the ev-9500gc-100 is sold in units of one. the ev-9200gf-100 comes in a set of five and is sold in one-unit sets.
469 appendix a development tools users manual u10105ej4v1um00 a.3.2 software sm78k0 (system simulator) this simulator simulates operations of the target system from a windows tm -installed host computer, enabling debuggung in c source level or assembler level. by using sm78k0, logical and performance verification processes can be performed independently of hardware development work without using ie-78000-r in-circuit emulator, which leads to reduction in development workload and improvement in software quality. this system simulator is used together with the df78064 device file (option). part number: m s sm78k0 sd78k/0 (screen debugger) this debugger is a program which controls the ie-78000-r in-circuit emulator from the host computer. the in-circuit emulator must be connected to the host computer via a serial interface (rs-232-c) cable. this debugger is used together with the df78064 device file (option). part number: m s sd78k0 df78064 (device file) (see note ) device file for the m pd78064 and 78064y subseries. this device file is used together with the sm78k0, cc78k/0, ra78k0, and sd78k/0 (option). part number: m s df78064 note this device file can be used for any of ra78k/0, cc78k/0, sm78k0, and sd78k/0. remark of the part number differs depending on the host machine and os used. refer to the table below. m s sm78k0 host machine os medium aa13 pc-9800 series ms-dos (ver. 3.30 - 5.00a) note 3.5-inch 2hd aa10 + windows (ver. 3.0 and 3.1) 5-inch 2hd ab13 ibm pc/at or refer to section a.4. 3.5-inch 2hc ab10 compatible machine 5-inch 2hc (on japanese windows) bb13 ibm pc/at or refer to section a.4. 3.5-inch 2hc bb10 compatible machine 5-inch 2hc (on english wondows) m s sd78k0 m s df78064 host machine os medium 5a13 pc-9800 series ms-dos 3.5-inch 2hd 5a10 (ver. 3.30 - 5.00a) note 5-inch 2hd 7b13 ibm pc/at or refer to section a.4. 3.5-inch 2hc 7b10 compatible machine 5-inch 2hc note the task swap function is not available with this software though the function is provided in ms-dos version 5.0 or later. *
470 appendix a development tools users manual u10105ej4v1um00 a.4 operating systems for ibm pc the following operating systems are available for ibm pc. if sm78k0 and fe9200 (see section b.2 "fuzzy inference development support system " ) are to be operated, windows version 3.0 or 3.1 is also required. os version pc dos version 3.3 through 6.3 j6.1/v through j6.3/v (see note ) ibm dos tm j5.02/v (see note ) ms-dos version 5.0 through 6.2 5.0/v through 6.2v (see note ) note supports english versions only. caution the task swap function is not available with this software though the function is provided in ms-dos version 5.0 or later. *
471 appendix a development tools users manual u10105ej4v1um00 system-up method from other in-circuit emulator to ie-78000-r when you already have an in-circuit emulator for the 78k series or the 75x series, you can use that in-circuit emulator as the equivalent of a 78k/0 in-circuit emulator ie-78000-r by replacing the internal break board with the ie-78000-r-bk. series name in-circuit emulator owned board to be purchased 75x series ie-75000-r*, ie-75001-r ie-78000-r-bk 78k/i series ie-78130-r, ie-78140-r 78k/ii series ie-78230-r*, ie-78230-r-a ie-78240-r*, ie-78240-r-a 78k/iii series ie-78320-r*, ie-78327-r ie-78330-r, ie-78350-r remark * : available for maintenance purpose only.
472 appendix a development tools users manual u10105ej4v1um00 item millimeters inches b 1.85?.25 0.073?.010 c 3.5 0.138 a 14.45 0.569 d 2.0 0.079 h 16.0 0.630 i 1.125?.3 0.044?.012 j 0~5 0.000~0.197 e 3.9 0.154 f 0.25 g 4.5 0.177 tgc-100sdw-g1e 0.010 k 5.9 0.232 l 0.8 0.031 m 2.4 0.094 n 2.7 0.106 item millimeters inches b 0.5x24=12 0.020x0.945=0.472 c 0.5 0.020 a 21.55 0.848 d 0.5x24=12 0.020x0.945=0.472 h 10.9 0.429 i 13.3 0.524 j 15.7 0.618 e 15.0 0.591 f 21.55 g 3.55 0.140 0.848 k 18.1 0.713 l 13.75 0.541 m 0.5x24=12.0 0.020x0.945=0.472 q 10.0 0.394 r 11.3 0.445 s 18.1 0.713 n 1.125?.3 0.044?.012 o 1.125?.2 p 7.5 0.295 0.044?.008 w 1.8 0.071 x c 2.0 c 0.079 y 0.9 0.035 t 5.0 0.197 u 5.0 v 4- 1.3 4- 0.051 0.197 z 0.3 0.012 f ff f f f f f f f ff h a b c i j k g f e d n o l m x p q r s u protrusion height w v k i m n z j g i h a e d c b y f x t note : product by tokyo eletech corporation. drawing for conversion adapter (tgc-100sdw) figure a-2. tgc-100sdw drawing (for reference only) (unit: mm)
473 appendix a development tools users manual u10105ej4v1um00 drawing and footprint for conversion socket (ev-9200gf-100) figure a-3. ev-9200gf-100 drawing (for reference only) ev-9200gf-100 a d e b f 1 no.1 pin index m n o l k s r q i h g p c j ev-9200gf-100-g0e item millimeters inches a b c d e f g h i j k l m n o p q r s 24.6 21 15 18.6 4-c 2 0.8 12.0 22.6 25.3 6.0 16.6 19.3 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.969 0.827 0.591 0.732 4-c 0.079 0.031 0.472 0.89 0.996 0.236 0.654 0.76 0.323 0.315 0.098 0.079 0.014 0.091 0.059 f f f f based on ev-9200gf-100 (1) package drawing (in mm)
474 appendix a development tools users manual u10105ej4v1um00 figure a-4. ev-9200gf-100 footprint (for reference only) f h e d a b c i j k l 0.026 1.142=0.742 0.026 0.748=0.486 ev-9200gf-100-p1e item millimeters inches a b c d e f g h i j k l 26.3 21.6 15.6 20.3 12 0.05 6 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 1.035 0.85 0.614 0.799 0.472 0.236 0.014 0.093 0.091 0.062 0.65 0.02 29=18.85 0.05 0.65 0.02 19=12.35 0.05 f +0.001 ?.002 +0.002 ?.002 +0.001 ?.002 +0.003 ?.002 +0.003 ?.002 +0.003 ?.002 +0.001 ?.001 +0.001 ?.002 f +0.001 ?.002 f f g f f based on ev-9200gf-100 (2) pad drawing (in mm) dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution
475 users manual u10105ej4v1um00 appendix b embedded software this section describes the embedded software which are provided for the m pd78064 and 78064y subseries to allow users to develop and maintain the application program for these subseries. b.1 real-time os (1/2) rx78k/0 rx78k/0 is a real-time os which is based on the m itron specification. real-time os supplied with the rx78k/0 nucleus and a tool to prepare multiple information tables (configurator). when using the rx78k/0, the ra78k/0 assembler package (option) is necessary. part number: m s rx78013- dddd caution when purchasing the rx78k/0, fill in the purchase application form in advance, and sign the use approval contract. remark and dddd of the part number differs depending on the host machine and os used. refer to the table below. m s rx78013- dddd dddd product outline max. no. for use in mass production 001 evaluation object do not use for mass production 100k mass-production object 100,000 001m 1,000,000 010m 10,000,000 s01 source program source program for mass-production object host machine os medium 5a13 pc-9800 series ms-dos 3.5-inch 2hd 5a10 (ver. 3.30 - 5.00a) note 5-inch 2hd 7b13 ibm pc/at or refer to section a.4. 3.5-inch 2hc 7b10 compatible machine 5-inch 2hc 3h15 hp9000 series 300 hp-ux (rel.7.05b) cartridge tape (qic-24) 3p16 hp9000 series 700 hp-ux (rel.9.01) digital tape (dat) 3k15 sparcstation sunos (rel.4.1.1) cartridge tape (qic-24) 3m15 ews-4800 series (risc) ews-ux/v (rel.4.0) note the task swap function is not available with this software though the function is provided in ms-dos version 5.0 or later. *
476 appendix b embedded software users manual u10105ej4v1um00 b.1 real-time os (2/2) mx78k0 os mx78k/0 is an os for subsets based on the m itron specification. supplied with the mx78k0 nucleus. this os manages tasks, events, and time. in task management operation, it controls the execution orders of tasks, and switches processing to the task to be executed next. part number: m s mx78k0- ddd remark and ddd of the part number differs depending on the host machine and os used. refer to the table below. m s mx78k0- ddd ddd product outline remark 001 evaluation object use for preproduction. xx mass-production object use for mass-production. s01 source program available only when purchasing mass- production object host machine os medium 5a13 pc-9800 series ms-dos 3.5-inch 2hd 5a10 (ver. 3.30 - 5.00a) note 5-inch 2hd 7b13 ibm pc/at or refer to section a.4. 3.5-inch 2hc 7b10 compatible machine 5-inch 2hc 3h15 hp9000 series 300 hp-ux (rel.7.05b) cartridge tape (qic-24) 3p16 hp9000 series 700 hp-ux (rel.9.01) digital tape (dat) 3k15 sparcstation sunos (rel.4.1.1) cartridge tape (qic-24) 3m15 ews-4800 series (risc) ews-ux/v (rel.4.0) note the task swap function is not available with this software though the function is provided in ms-dos version 5.0 or later. *
477 appendix b embedded software users manual u10105ej4v1um00 b.2 fuzzy inference development support system fe9000/fe9200 (fuzzy knowledge data creation tool) program supporting input of fuzzy knowledge data (fuzzy rule and membership function), editing (edit), and evaluation (simulation). fe9200 operates on windows. part number: m s fe9000 (pc-9800 series) m s fe9200 (ibm pc/at or compatible machine) ft9080/ft9085 (translator) program converting fuzzy knowledge data obtained by using fuzzy knowledge data preparation tool to ra78k/0 assembler source program. part number: m s ft9080 (pc-9800 series) m s ft9085 (ibm pc/at or compatible machine) fi78k0 (fuzzy inference module) program executing fuzzy inference. fuzzy inference is executed by linking fuzzy knowl- edge data converted by translator. part number: m s fi78k0 (pc-9800 series, ibm pc/at or compatible machine) fd78k0 (fuzzy inference debugger) support software evaluating and adjusting fuzzy knowledge data at hardware level by using in-circuit emulator. part number: m s fd78k0 (pc-9800 series, ibm pc/at or compatible machine) remark of the part number differs depending on the host machine and os used. refer to the table below. m s fe9000 m s ft9080 m s fi78k0 m s fd78k0 host machine os medium 5a13 pc-9800 series ms-dos 3.5-inch 2hd 5a10 (ver. 3.30 - 5.00a) note 5-inch 2hd m s fe9200 m s ft9085 m s fi78k0 m s fd78k0 host machine os medium 7b13 ibm pc/at refer to section a.4. 3.5-inch 2hc 7b10 or compatible machine 5-inch 2hc note the task swap function is not available with this software though the function is provided in ms-dos version 5.0 or later.
478 users manual u10105ej4v1um00 [memo]
479 users manual u10105ej4v1um00 appendix c register index c.1 register name index [a] a/d converter input select register (adis) ... 224 a/d converter mode register (adm) ... 222 a/d conversion result register (adcr) ... 221 asynchronous serial interface status register (asis) ... 345, 354 asynchronous serial interface mode register (asim) ... 343, 351, 353, 366 [b] baud rate generator control register (brgc) ... 346, 355, 367 [c] capture/compare control register 0 (crc0) ... 139 capture/compare register 00 (cr00) ... 134 capture/compare register 01 (cr01) ... 134 clock timer mode control register (tmc2) ... 199 compare register 10 (cr10) ... 177 compare register 20 (cr20) ... 177 [e] 8-bit timer mode control register (tmc1) ... 180 8-bit timer output control register (toc1) ... 181 8-bit timer register 1 (tm1) ... 177 8-bit timer register 2 (tm2) ... 177 external interrupt mode register 0 (intm0) ... 142, 409 external interrupt mode register 1 (intm1) ... 225, 409 [i] interrupt mask flag register 0h (mk0h) ... 407 interrupt mask flag register 0l (mk0l) ... 407 interrupt mask flag register 1l (mk1l) ... 407, 424 interrupt request flag register 0h (if0h) ... 406 interrupt request flag register 0l (if0l) ... 406 interrupt request flag register 1l (if1l) ... 406, 424 interrupt timing specification register (sint) ... 248, 266, 284, 301, 311, 321 [k] key return mode register (krm) ... 109, 425
480 appendix c register index users manual u10105ej4v1um00 [l] lcd display control register (lcdc) ... 376 lcd display mode register (lcdm) ... 374 [m] memory size switching register (ims) ... 440 [o] oscillation mode select register (osms) ... 117 oscillation stabilization time select register (osts) ... 428 [p] port 0 (p0) ... 92 port 1 (p1) ... 94 port 2 (p2) ... 95, 97 port 3 (p3) ... 99 port 7 (p7) ... 100 port 8 (p8) ... 102 port 9 (p9) ... 103 port 10 (p10) ... 104 port 11 (p11) ... 105 port mode register 0 (pm0) ... 106 port mode register 1 (pm1) ... 106 port mode register 2 (pm2) ... 106 port mode register 3 (pm3) ... 106, 141, 182, 213, 218 port mode register 7 (pm7) ... 106 port mode register 8 (pm8) ... 106 port mode register 9 (pm9) ... 106 port mode register 10 (pm10) ... 106 port mode register 11 (pm11) ... 106 priority specification flag register 0h (pr0h) ... 408 priority specification flag register 0l (pr0l) ... 408 priority specification flag register 1l (pr1l) ... 408 processor clock control register (pcc) ... 115 pull-up resistor option register h (puoh) ... 109 pull-up resistor option register l (puol) ... 109 [r] receive buffer register (rxb) ... 341 receive shift register (rxs) ... 341
481 appendix c register index users manual u10105ej4v1um00 [s] sampling clock select register (scs) ... 143, 411 serial bus interface control register (sbic) ... 246, 252, 264, 283, 299, 305, 310, 320 serial i/o shift register 0 (sio0) ... 240, 294 serial operating mode register 0 (csim0) ... 244, 250, 263, 282, 298, 304, 309, 319 serial operating mode register 2 (csim2) ... 342, 350, 352, 365 16-bit timer mode control register (tmc0) ... 137 16-bit timer output control register (toc0) ... 140, 147, 149 16-bit timer register (tm0) ... 134 slave address register (sva) ... 240, 286, 294 successive approximation register (sar) ... 221 [t] timer clock select register 0 (tcl0) ... 135, 211 timer clock select register 1 (tcl1) ... 178 timer clock select register 2 (tcl2) ... 196, 204, 216 timer clock select register 3 (tcl3) ... 242, 296 transmit shift register (txs) ... 341 [w] watchdog timer mode register (wdtm) ... 206
482 appendix c register index users manual u10105ej4v1um00 c.2 register symbol index [a] adcr: a/d conversion result register ... 221 adis: a/d converter input select register ... 224 adm: a/d converter mode register ... 222 asim: asynchronous serial interface mode register ... 343, 351, 353, 366 asis: asynchronous serial interface status register ... 345, 354 [b] brgc: baud rate generator control register ... 346, 355, 367 [c] cr00: capture/compare register 00 ... 134 cr01: capture/compare register 01 ... 134 cr10: compare register 10 ... 177 cr20: compare register 20 ... 177 crc0: capture/compare control register 0 ... 139 csim0: serial operating mode register 0 ... 244, 250, 263, 282, 298, 304, 309, 319 csim2: serial operating mode register 2 ... 342, 350, 352, 365 [i] if0h: interrupt request flag register 0h ... 406 if0l: interrupt request flag register 0l ... 406 if1l: interrupt request flag register 1l ... 406, 424 ims: memory size switching register ... 440 intm0: external interrupt mode register 0 ... 142, 409 intm1: external interrupt mode register 1 ... 225, 409 [k] krm: key return mode register ... 109, 425 [l] lcdc: lcd display control register ... 376 lcdm: lcd display mode register ... 374 [m] mk0h: interrupt mask flag register 0h ... 407 mk0l: interrupt mask flag register 0l ... 407 mk1l: interrupt mask flag register 1l ... 407, 424
483 appendix c register index users manual u10105ej4v1um00 [o] osms: oscillation mode select register ... 117 osts: oscillation stabilization time select register ... 428 [p] p0: port 0 ... 92 p1: port 1 ... 94 p2: port 2 ... 95, 97 p3: port 3 ... 99 p7: port 7 ... 100 p8: port 8 ... 102 p9: port 9 ... 103 p10: port 10 ... 104 p11: port 11 ... 105 pcc: processor clock control register ... 115 pm0: port mode register 0 ... 106 pm1: port mode register 1 ... 106 pm2: port mode register 2 ... 106 pm3: port mode register 3 ... 106, 141, 182, 213, 218 pm7: port mode register 7 ... 106 pm8: port mode register 8 ... 106 pm9: port mode register 9 ... 106 pm10: port mode register 10 ... 106 pm11: port mode register 11 ... 106 pr0h: priority specification flag register 0h ... 408 pr0l: priority specification flag register 0l ... 408 pr1l: priority specification flag register 1l ... 408 puoh: pull-up resistor option register h ... 109 puol: pull-up resistor option register l ... 109 [r] rxb: receive buffer register ... 341 rxs: receive shift register ... 341 [s] sar: successive approximation register ... 221 sbic: serial bus interface control register ... 246, 252, 264, 283, 299, 305, 310, 320 scs: sampling clock select register ... 143, 411 sint: interrupt timing specification register ... 248, 266, 284, 301, 311, 321 sio0: serial i/o shift register 0 ... 240, 294 sva: slave address register ... 240, 286, 294
484 appendix c register index users manual u10105ej4v1um00 [t] tcl0: timer clock select register 0 ... 135, 211 tcl1: timer clock select register 1 ... 178 tcl2: timer clock select register 2 ... 196, 204, 216 tcl3: timer clock select register 3 ... 242, 296 tm0: 16-bit timer register ... 134 tm1: 8-bit timer register 1 ... 177 tm2: 8-bit timer register 2 ... 177 tmc0: 16-bit timer mode control register ... 137 tmc1: 8-bit timer mode control register ... 180 tmc2: clock timer mode control register ... 199 toc0: 16-bit timer output control register ... 140, 147, 149 toc1: 8-bit timer output control register ... 181 txs: transmit shift register ... 341 [w] wdtm: watchdog timer mode register ... 206
485 users manual u10105ej4v1um00 appendix d revision history the revision history is shown below. the chapters appearing in the revised-chapter column indicate those of the corresponding edition. (1/5) edition major changes revised chapter second development of the m pd78063 and m pd78064 has now been completed. throughout m pd78p064kl-t: being planned -> being developed operating supply voltage range: 2.7 to 6.0 v -> 2.0 to 6.0 v chapter 1 input/output circuit type of pins p10/ani0 to p17/ani7: 9-b -> 11 chapter 2 recommended connection of unused ic pins (masked-rom product): connect to v ss . -> connect to v ss directly. figure 5-2 has been added. chapter 5 the wiring diagram of the oscillator has been modified. table 6-5 has been modified. chapter 6 a note has been added to timer clock selection register 0 format. a caution has been added to 16-bit timer mode control register format. (6) and (7) have been added to section 6.5 . tables 8-1 and 8-3 have been modified. chapter 8 a note has been added to timer clock selection register 0 format. chapter 10 a note has been added to a/d converter mode register format. chapter 12 port mode register 2 (pm2) has been added to table 13-2 . chapter 13 serial interface channel 0 block diagram has been modified. serial operating mode register 0 format has been modified. serial bus interface control register format has been modified. interrupt timing specification register format has been modified. figure 13-7 has been modified. figures 13-20 and 13-21 have been modified. table 13-3: <3> reception of address signal has been added as the condition for output of the ready signal. (e) has been added to (10) of section 13.4.3 . figure 13-31 has been modified.
486 appendix d revision history users manual u10105ej4v1um00 (2/5) edition major changes revised chapter second serial interface channel 2 block diagram has been modified. chapter 14 serial operating mode register 2 format has been modified. asynchronous serial interface mode register format has been modified. table 14-2 has been modified. (3) has been added to section 14.4.2 . a note has been added to interrupt request flag register format. chapter 16 a note has been added to interrupt mask flag register format. table 16-3 has been modified. figures 16-15 and 16-16 have been modified. table 17-1 has been modified. chapter 17 a remark has been added to figure 17-2 . table 17-3 has been modified. language processing software, debugging tools, and development appendix a tool configurations have been modified. system upgrade method to an ie-78000-r system from other in-circuit emulators has been added. drawing and footprint for conversion socket (ev-9200gf-100) has been added. appendix b has been added. appendix b
487 appendix d revision history users manual u10105ej4v1um00 (3/5) edition major changes revised chapter third development of the m pd78062gc, m pd78062gf, m pd78p064gc, and throughout m pd78p064gf has already been completed. section 1.6 has been changed. chapter 1 section 2.2.22 has been modified. chapter 2 the cautions given in sections 4.2.3 and 4.2.5 have been modified. chapter 4 table 4-3 has been added. a caution has been added to (2) of section 5.3 . chapter 5 table 5-2 has been modified. a caution has been added to section 5.6.2 . timer clock selection register 0 format has been modified. chapter 6 chapter 10 tables 6-2 and 6-6 have been modified. chapter 6 tables 6-3 and 6-7 have been modified. a caution has been added to (2) of section 6.3 . cautions have been added to (3) and (4) of section 6.4.4 . figure 6-32 has been modified. figure 6-34 has been modified. a caution has been added to timer clock selection register 1 format. chapter 7 table 7-7 has been added. timer clock selection register 2 format has been modified. chapter 8 chapter 9 chapter 11 in section 12.5 , (6) a/d conversion end interrupt request flag chapter 12 (intad) has been changed to (6) interrupt request flag (adif). also, (8) has been deleted. a note has been deleted from table 13-1 . chapter 13 a caution has been added to timer clock selection register 3 format. serial bus interface control register format has been modified. figure 13-21 has been modified. table 14-2 has been modified. chapter 14 (3) has been added to section 14.4.3 .
488 appendix d revision history users manual u10105ej4v1um00 (4/5) edition major changes revised chapter third the 1/2 bias method has been modified in the lcd drive power supply chapter 15 connection examples (with on-chip split resistor and with external split resistor). the following lcd drive waveform examples have been modified: static lcd drive waveform examples 2-time-division lcd drive waveform examples (1/2 bias method) 3-time-division lcd drive waveform examples (1/2 bias method) 3-time-division lcd drive waveform examples (1/3 bias method) 4-time-division lcd drive waveform examples (1/3 bias method) chapter 16 "interrupt functions has been changed to chapter 16 chapter 16 "interrupt and test functions . section 16.5 has been added. a caution relating to be specification of the writing address has been chapter 19 added to section 19.2 . sections 20.2 and 20.3 have been deleted. chapter 20 version of pc dos: 3.1 -> 3.3 to 5.0 appendix a,b the 3.5-inch 2hc floppy disk format has been added to the supported distribution media for the ibm pc/at. drawing for conversion adapter (ev-9500gc-100) has been appendix a added. the fuzzy inference development support system has been changed. appendix b appendix c of the previous version has been deleted. appendix c has been newly added. appendix c
489 appendix d revision history users manual u10105ej4v1um00 (5/5) edition major changes revised chapter fourth m pd78064y subseries has been added for target devices. throughout ? recommended connections of the following unused pins has been modified. chapter 3 p07/xt1, p110 to p117, v pp ? i/o circuit type of the following pins has been modified. p110 to p117 a caution given in figure 7-4 has been modified and added. chapter 7 a caution given in figure 7-6 has been modified. figure 10-1 has been modified. chapter 10 figure 14-2 has been modified. chapter 14 section 14.5(7) has been modified and figure 14-12 has been added. figure 15-4 has been modified. chapter 15 figure 15-21 has been modified. section 15.4.4(c) has been modified. figure 15-34 has been modified. figure 17-1 has been modified. chapter 17 range of baud rate transmit/receive clock generated by main systm clock has been changed. 75 bps to 38400 bps -> 75 bps to 76800 bps table 20-1 has been modified. chapter 20 description of operation conditions in halt mode has been separated to those under main system clock operation and sub- system clock operaion. cautions given in section 20.2.2(1) have been modified. table 20-3 has been modified. description of operation conditions in stop mode has been separated to those under main system clock operation and sub- system clock operaion. description of qtop microcontroller has been added to section 22.5. chapter 22 hp9000 series 700 has been added to the host machine for development appendix a, b tools and embedded software. system simulator (sm78k0) has been added for development tools. appendix a section a.4 has been added. os(mx78k0) has been added for embedded software. appendix b
490 users manual u10105ej4v1um00 [memo]
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